Planar Silicon on Insulator (SOI) Transistor Models
Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide. Uses include microprocessor design, high-frequency RF applications, and silicon photonics.
L-UTSOI: v102.9.0, L-UTSOI: v102.8.0 – Developer: CEA-LETI
L-UTSOI compact model is dedicated to FDSOI technologies, and is the new name of Leti-UTSOI, a high maturity model in development since 2007 and used in industrial environments for nearly 8 years. It continues to benefit from experience accumulated over several industrial technology generations, as well as from more than 25 years of CEA-Leti expertise on FDSOI technology. The L-UTSOI model is able to physically describe FDSOI transistor behavior for any bias configuration, including the case of strong forward back bias where two channels take place at the front and back interfaces of a thin silicon body. Such capability relies on innovative solutions for surface potential analytical calculations and for describing current and charge models.
BSIM-SOI: v4.7.0 – Developer: UC Berkeley
A CMC standard model for SOI (Silicon-On-Insulator) circuit design is called BSIM-SOI. The foundation of this model is the BSIM3 framework. Because it uses the same fundamental formulas as the bulk model, BSIM3v3’s smoothness and physical characteristics are preserved. To guarantee parameter compatibility, the majority of generic MOSFET operating (non-SOI specific) parameters are directly transferred from BSIM3V3.
BSIM-SOI: v100.1.1 – Developer: UC Berkeley
A new CMC standard model for SOI (Silicon-On-Insulator) circuit design is called Symmetric BSIM-SOI. A novel core for dynamic depletion operation for SOI devices with moderate doping is included in this model. Additionally, it provides the PDSOI operation, which is developed on top of the BSIM-BULK framework. In order to preserve the physical properties and smoothness, it uses the same fundamental formulas as the bulk model for PDSOI technology. Most parameters related to general MOSFET operation (non-SOI specific) are directly imported from BSIM-BULK to ensure parameter compatibility. The model provides excellent accuracy compared to measured data in all regions of operation. It features model symmetry valued for analog and RF applications.
HiSIM_SOI: v1.5.0 – Developer: Hiroshima University
The compact SOI-MOSFET model HiSIM-SOI based on the complete surface-potential description. The model considers all possible charges induced in the device for the formulation of the Poisson equation, which is solved iteratively. Thus HiSIM-SOI is valid for any structural variations from thick to extremely thin SOI or BOX layers, and the dynamic depletion between the fully and partially depleted conditions is well reproduced.
HiSIM_SOTB: v1.3.0 – Developer: Hiroshima University
HiSIM-SOTB accurately replicates the characteristics of the SOTB-MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a practical transistor structure for super-low-power-consumption, by lowering the operating voltage of integrated circuits. HiSIM-SOTB enables the accurate simulation of circuit operations in the case of substantially lowered supply voltages for transistor operation, ranging from 1 V to 0.4 V.