HPC Archives - RISC-V International
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HPC
High Performance Computing (HPC) refers to using powerful, interconnected processors to solve complex problems quickly. In the RISC-V ecosystem, it means building open, flexible systems that can scale for demanding tasks like scientific research, AI training, and data analysis.
Feb
17
Support RAJA and Scientific Applications on RVV Architectures
By
RISC-V International Staff
Featured Work
Project Snapshot In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. RAJA is a C++ library primarily developed…
Feb
13
RISC-V Now! by Andes | Hsinchu
By
Abhi Arora
RISC-V Now! is the conference focused on turning RISC-V standards into products that ship — where spec goes to scale. Built for Practitioners RISC-V Now! addresses the realities of moving…
Feb
13
RISC-V Now! by Andes | Shanghai
By
Abhi Arora
RISC-V Now! is the conference focused on turning RISC-V standards into products that ship — where spec goes to scale. Built for Practitioners RISC-V Now! addresses the realities of moving…
Feb
13
RISC-V Now! by Andes | Beijing
By
Abhi Arora
RISC-V Now! is the conference focused on turning RISC-V standards into products that ship — where spec goes to scale. Built for Practitioners RISC-V Now! addresses the realities of moving…
Dec
10
Ocelot3: Full Vector “V” Extension for BOOM
By
RISC-V International Staff
Featured Work
Project Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The decoupled VPU is connected through…
Nov
12
We’re Showcasing RISC-V at SC25, the World’s Largest Supercomputing Conference
By
Nick Brown
Viewpoints
I’m heading to SC25 in St. Louis next week to advocate for the growing role of RISC-V in high-performance computing (HPC), alongside my peers in the RISC-V HPC special interest…
Jul
07
Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor Computing
By
Anisha Sharma
In the Media
San Jose, CA – July 7, 2025 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), the leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announced…
May
30
Aion Silicon wins $12M deal for RISC-V HPC, AI design work
By
Anisha Sharma
In the Media
End-to-end ASIC partnership to accelerate global supercomputing market with open-standard, energy-efficient silicon. Aion Silicon announced it has secured a $12 million engagement to provide comprehensive design services for a confidential customer developing next-generation…
Apr
23
Andes teams on FPGA prototyping for RISC-V development
By
Anisha Sharma
In the Media
Andes Technology has teamed with S2C to develop an FPGA-based prototyping system for its latest RISC-V cores with extensions. The strategic deal uses S2C’s new Prodigy S8-100 FPGA prototyping platform,…
Apr
16
Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
By
Anisha Sharma
In the Media
San Jose, CA – April 23, 2025 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), the leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International,…
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