(PDF) Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation in Grid-Connected Inverter

Received 3 December 2022, accepted 2 January 2023, date of publication 25 January 2023, date of current version 9 February 2023. Digital Object Identifier 10.1109/ACCESS.2023.3239662 Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation in Grid-Connected Inverter GARBA ELHASSAN1,2 , SHAMSUL AIZAM ZULKIFLI 1 , SOLOMON ZAKWOI ILIYA2,3 , (Member, IEEE), ZAINAB YUNUSA4 , (Member, IEEE), MOHAMMED AHMED5 , MUBASHIR HAYAT KHAN1 , AND RONALD JACKSON1 1 Department of Electrical Power Engineering, Faculty of Electrical and Electronics Engineering, Universiti Tun Hussein Onn Malaysia (UTHM), Parit Raja, Batu Pahat, Johor 86400, Malaysia 2 National Space Research and Development Agency, Obasanjo Space Centre, Lugbe, Abuja 900107, Nigeria 3 Institute of Space Science and Engineering, African University of Science and Technology, Galadimawa, Abuja 900109, Nigeria 4 Department of Electrical Engineering, University of Hafr Al Batin, Hafr Al Batin 39524, Saudi Arabia 5 Department of Electrical Engineering, Abubakar Tafawa Balewa University, Lushi, Bauchi 740272, Nigeria Corresponding authors: Garba Elhassan (

) and Shamsul Aizam Zulkifli (

) This work was supported in part by Universiti Tun Hussein Onn Malaysia, in part by the UTHM Publisher’s Office via Publication Fund under Grant E15216, and in part by the Advanced Aircraft Engineering Laboratory, National Space Research and Development Agency, Nigeria. ABSTRACT The control of voltage source converters (VSCs) is now implemented on digital micropro- cessors. This digitalization has the drawback of time delay in the control loop. The goal of this research work was to investigate improvements that can be obtained from the combination of model-based and model-free time-delay compensation approaches. Deadbeat control (DBC) from model-based techniques and the method of moving the control variable’s sampling instants, or the pulse-width modulation (PWM) updating instants, from model-free time-delay compensation techniques, were put together as the proposed new method of time-delay compensation in this study. These controllers were thoroughly examined in terms of control algorithm design, system stability analysis, and sensitivity analysis of plant parameter perturbations. In addition, thorough Simulink-based computer simulations were conducted in this work to assess the performance of each controller. The proposed method compensated about 80 µs as compared with the time delay compensated by the conventional single-sampling method. This research work was limited to simulations only; hence, conducting experiments to further validate this research work could be a direction for further research. INDEX TERMS Current controllers, DB control time delay, grid-connected converters. I. INTRODUCTION devices with short-time-delay controllers in order to compete Over the last sixty years, the field of power electronics has in the market. progressed. Static converters can now effectively transform There are a number of power quality problems at present, electric energy to fulfill the needs of a wide range of appli- which can be classified into natural and man-made. Natural cations and they are the technology that allows renewable causes of poor power quality are mainly faults, lightning, energy to be integrated into electric grids. As a result, power storms, and equipment failure. Man-made causes are mainly electronics will be crucial in the renovation of existing elec- related to loads or system operations. One of the most sig- tric grids. Grid codes are updated on a regular basis by system nificant issues with power quality is the presence of harmon- operators to ensure power quality and grid security. As a ics, which can be caused by a variety of loads that operate result, power converter manufacturers must build reliable in a nonlinear fashion. These loads can range from more traditional ones, such as transformers, electrical machines, The associate editor coordinating the review of this manuscript and and furnaces, to more modern ones, such as power con- approving it for publication was Inam Nutkani . verters, switched-mode power supplies (SMPS), AC voltage This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 12444 VOLUME 11, 2023 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation controllers, and so on [1]. It is commonly known that dis- cause the controller’s performance to deteriorate, as well as tributed generation, in spite of the advantages it offers, results instability. in harmonic issues as a direct result of power converter Therefore, the consequences of time delay may be miti- interfaces. From the inverter side, passive filters, such as L, gated by using compensators in certain situations. A large LC, LCL, and LCCL filters and so on, are used to limit number of time-delay compensation approaches have been the harmonic injection, while active filters (AF) are used suggested in the recent literature, most notably in [15], where for harmonic and reactive power compensation between the the authors used dual sampling and updating as well as a pro- inverter and the grid or between the grid and nonlinear loads. portional resonant controller to eliminate the computational A comprehensive discussion on recent AFs used was pre- delay in the control loop. A good result was achieved in this sented in [2]. In [3], the authors proposed harmonic miti- research work; however, this method can be enhanced further gation using the phase shift. According to the authors, this by adopting a higher number of sampling and updating. There technique has the ability for harmonic self-cancellation. is a detailed explanation of this topic in [9], where the authors In recent research works reported in [4], [5], and [6], the reviewed and classified all the compensation techniques for major emphasis was on converter control techniques. This time delay. Additionally, the authors hypothesized that com- control strategy incorporates cascade control, which may bining two of the best compensation techniques, which are the either be the inner loop or outer loop control, or both, being technique of shifting the sampling and updating instants from applied in a single system. The inner loop control usually the model-free approach and the DBC technique from the adopts current control because the inner current loop is much model-based compensation approach, can be a new improved faster in controlling system dynamics than does outer voltage method to give better results. These two techniques have or power loop control. As a result, the current control loop, been reported separately in the literature to have an outstand- also known as the inner control loop, plays a very signifi- ing performance, where the DBC with double sampling and cant role in enhancing the overall performance of a control updating was researched in [16]. system. However, typical current controllers that are used Deadbeat current control has the advantages of achieving in the inner control loop, such as the proportional-integral- zero steady-state error, fast dynamic response, and time-delay derivative (PID) controller in the synchronous frame, are mitigation [9], [10], but the downsides of this controller are its often constrained by the amount of useful bandwidth that is aggressiveness to control actions, sensitivity to model accu- available in the controller [7], [8]. racy, and inherent one-period delay. These drawbacks reduce The control of grid-connected inverters is now imple- its potential of achieving fast current tracking and resilience mented digitally on a microprocessor as a result of the to disturbances. In the literature, a state observer has been advances achieved so far in digital signal processing. used to lessen the controller’s sensitivity to model accu- Although, some problems have been reported in the literature racy, while the technique of shifting sampling and updating regarding the digital implementation, which limits the per- instants has been used to mitigate the time delay associated formance of the system. Among them are the occurrence of with the controller. However, to the best of our knowledge, time delay in the control loop, the existence of a ripple com- no studies have looked into the issue of the aggressiveness of ponent at the sampling frequency, harmonics in the output, this controller. Additionally, among the methods of shifting and restrictions on the useable bandwidth, which are limited sampling and updating instants for time-delay mitigation, to a fraction of the sampling frequency [11]. However, for the single-sampling single-updating (SS-SU) and the double- various practical reasons, digital controllers have reported sampling double-updating (DS-DU) methods are associated strong benefits that exceed the disadvantages described, to the with a one-period time delay and a half-period time delay, point that digital controllers are more desired, particularly respectively [16]. On the other hand, while the multisampling in grid-connected inverter applications. As a consequence of multi-updating method eliminates the residual time delay this, research on digital controllers, such as DBCs, is now associated with SS-SU and DS-DU, it introduces some non- receiving more attention than it did in the past, as stated linearities, requiring the use of an anti-aliasing filter in the in [10]. feedback path. The filter added re-introduces a phase lag, Before delving into the topic, it is very necessary to have a which compromises the dynamic benefits obtained by the solid understanding of the factors that lead to the inclusion MS-MU method [17]. Hence, a method that uses a tuning of time delay in the inverter’s control loop. The delay is polynomial to lessen the aggressiveness of the DBCC, models primarily caused by the zero-order hold effect associated with the controller with a time delay to reduce its sensitivity to digital pulse-width modulation [12], the controller computing model accuracy, and uses quadruple sampling and updating time [13], and the sampling and updating of the voltage and to reduce the inherent time delay was proposed in this study. current values to be controlled [14]. Therefore, when there The proposed method eliminates the need for the anti-aliasing is a significant amount of time lag in the control loop, the filter used in MS-MU and provides an improvement in time- controller is unable to function effectively. This might result delay mitigation as compared with that of the DS-DU method. in a controller with a decreased transient response, significant Additionally, different than what had been researched, our overshoot, and a narrow control bandwidth. This impact may work re-designed and investigated the best four approaches of VOLUME 11, 2023 12445 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation the DBC design reported in [10]. These four approaches were intuitively re-designed with time-delay consideration, and an investigation of the number of sampling that can give optimal time-delay compensation was also intuitively conducted in this study, as recommended in [9]. In the end, our proposed combined design can successfully be implemented on micro- controllers, with a relatively similar performance as that of the design implemented on the FPGA in [17]. The remaining parts of this article are structured as described below: time- delay compensation techniques are discussed in Section II, DBC design approaches with time delay are explained in Section III, and the stability analysis of the current controllers is offered in Section IV of this paper. Simulation results can be found in Section V, and in the last part of this report, which is Section VI, the conclusion and some suggestions are offered. Acknowledgment is documented in Section VII. FIGURE 1. (a) Single updating, (b) double updating, and (c) multi-updating. II. TIME-DELAY COMPENSATION TECHNIQUES Physical systems with the time delay characteristic are those whose responses to external stimuli are delayed regarding the impact on the systems’ output. [18]. Several time-delay in one pulse period. Similarly, more than five sampling compensation strategies have been presented in the literature, and updating points are seen in multi-sampling and multi- categorized as model-based (MB) or model-free (MF) [6]. updating, as shown in Fig. 1(c). Single sampling and updating MB techniques are more precise but reliant on the correctness will often result in a delay of one switching period, which of the system model, while MF techniques are less precise will place a restriction on the bandwidth that is accessible to but independent of the model’s accuracy. Examples of MB the current controller. By using the double-updating mode, time-delay compensation methods are the Smith predictor as seen in Fig. 1(b), the one-switching-period delay may be (SP), the modified Smith predictor (MSP), the deadbeat con- further decreased until it is equivalent to only half of the troller (DBC), and the model predictive controller (MPC), switching period. In this mode, the parameters are sampled among others. Examples of MF methods, on the other hand, twice, and the update is performed at the peak and valley included the damping technique (DT), the filter-based tech- of the triangular carrier twice: in the middle of the turn-on nique (FBT), and the technique of shifting the sampling time and in the middle of the turn-off time of the pulse width. instants (SSI) of the control variable [6]. Short delays may Additionally, updates are carried out at the peak and valley be compensated for using a range of techniques, as detailed of the triangular carrier. However, a number of scholars have in [9]. In the present research work, basically we combined proposed that, to further reduce time delay, the instant at both the MB and MF compensation methods, which were the which a control variable is sampled needs to be relocated DBC technique and the technique of shifting the sampling closer to the instant at which the duty cycle changes. This and updating instants of the control variable. In the next sub- method was used in [19], [20], and [21]. However, because section, the approach of shifting the sampling and updating of the asynchronous sampling process, utilizing this method instants (SSI) of the control variable is discussed. may result in harmonic content that is not acceptable [22]. The authors in [9] used the method of sampling control A. SHIFTING SAMPLING INSTANTS OF CONTROL variables around the duty cycle’s updating instants, despite VARIABLE OR PWM UPDATING INSTANTS the fact that conventional sampling in the middle of the turn- It is common to sample state variables during PWM on/off on and turn-off phases of the PWM would have minimized times. Inductor, capacitor, and grid currents are measured harmonic disturbances more effectively. Another method for in this manner, as shown in Fig. 1(a), where ms is the reducing time delay is to sample the state control variables single-updated pulse-width modulation (PWM) wave. The and perform several updates to the duty cycle within a single single-updated PWM wave ms (k − 1) of the (k − 1)th carrier switching period, as shown in Fig. 1(c). This method is called cycle is usually loaded at the peak of the (k − 1)th trian- the multi-sampling multi-updating approach [17]. This tech- gular carrier and the duty cycle is expressed as M (K) = nique may be readily implemented on field-programmable ms (k − 1), where ms (k − 1) is the duty cycle, which is gate arrays (FPGAs) [23]. calculated by sampling the values at the peak of the (k − 1)th triangular carrier [16]. Fig. 1(a) shows single sampling and 1) DIGITAL AND PWM DELAYS updating, with one sampling point and one updating point For a voltage-source converter (VSC) that is digitally con- in the pulse period; Fig. 1(b) shows doubling sampling and trolled, there will be a computing delay in addition to the updating, where there are two sampling and updating points PWM delay. The delay in computing is caused by the passage 12446 VOLUME 11, 2023 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation TABLE 1. Inverter parameters. FIGURE 2. (a) Sampling, (b) updating, and (c) firing signals. of time between the moment the current is sampled and instant k + 1, when the digital controller’s output voltage where Ts represents the digital sampling time, while Tsw reference signal is actually adjusted. This passage of time is represents the PWM sampling time. The condition of Tsw = denoted by the symbol k in Fig. 2, and it is shown as a time 0.5T s exists when synchronous PWM sampling is taken into difference from k to k+1. The digital sample’s instants shown account. PWM digital sampling is represented by T1s . in Fig. 2 are updated at the moment the PWM triangular carrier signal is in the midst of its cycle. This method is known III. DBC DESIGN APPROACHES WITH TIME DELAY as synchronous pulse-width modulation sampling, and the For the purpose of comparison, this study used a grid- digital computing delay, in this case, is equivalent to one sam- connected inverter equipped with an LCL filter and active ple period, shown as the gray band in Fig. 2. The zero-order damping, as presented in [26]. Fig. 3 depicts the control loop hold (ZOH) effect is the primary factor that contributes to of the inverter using grid-side current control with feedback PWM delay. This effect ensures that the PWM reference of capacitor current for the active-damping LCL filter, where value remains unchanged (solid-blue curve in Subplot (b) of PL represents the third-order filter and Kpwm represents the Fig. 2) after it has been modified, and the expression can be gain of the full-bridge three-phase inverter [27], which can described as follows [15], [24], [25]: be approximated by Equation 4: 1 − e−sTs Udc Gpwm (s) = (1) Kpwm = (4) s 2 The dashed-blue curve in Subplot (b) of Fig. 2 illustrates Equation 5 may be used to express the control system’s visually the averaged value of the PWM reference constant loop gain, which can be found in Fig. 4. that is kept on after each update. By considering the ZOH Ig impact of PWM, the gold accent band displays the approxi- Td(s) = Udc mated half-sample cycle delay. The following is a mathemat- Kpwm ical derivation of this approximation [19]: = h i h i e−1.5Ts s s3 Li Lg′ Cf +s2 Kpwm kd Cf Lg′ +s ′ Li + Lg 1 − e−jωTs sin (0.5ωTs ) −j0.5ωTs Gpwm (jω) = = e (5) jω 0.5ω = Ts e−j0.5ωTs (2) where, Lg′ = Lg + Lgs and Ts is the sampling time. The total digital delay, Gd(s), after taking into account To evaluate the combined time-delay compensation tech- sampling, calculating, updating, and the ZOH impact of niques, we used the plant transfer function modelled with PWM, may be determined as: time delay, as prescribed in Equation 5. The assumption that the grid voltage is an ideal voltage source may be made for 1 frequencies other than the fundamental, and the grid side can Gd (s) = e−Ts s Ts e−j0.5ωTs = e−1.5Ts s (3) Ts be considered as if it were a short circuit [28]. VOLUME 11, 2023 12447 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation FIGURE 3. Block diagram of grid-side current control with active damping and time delay. FIGURE 4. Step and Nyquist plots for (a, b) PZCNRA, (c, d) PZCMRA, (e, f) FRA, (g, h) SVDA, and (i, j) HBDA at steady state. As a result, based on Table 1, the transfer function from Discretization was carried out utilizing the ZOH approach, Equation 5 can be represented as Equation 6, which becomes and the sampling frequency was set at 10 kHz. The discrete the plant to be controlled. version of the transfer function in Equation 7, as shown at the bottom of the next page. 340 As can be seen from the zero-pole gain (zpk) in Equation 7, Td(s) = e−1.5Ts s 2.006e−11 s3 + 4.702e−7 s2 + 0.005512s the system had one zero, which was located outside of the (6) unit circle, as well as one pole, which was located on the unit 12448 VOLUME 11, 2023 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation cycle. As a result, a discrete controller must be designed to and presented as in Equation 12: force the pole to lie within the unit circle. Because the dead- 0.0781(z + 11.81) beat controller’s design processes were given in d-operator N(z) = (12) z−1 , Equation 7 can be represented as Equation 8, as shown z2 at the bottom of the page, by simply dividing the zpk by z. The step plot and Nyquist plot are shown, respectively, Then, using the formulas presented in [7], we developed the in Fig. 4’s Subplots (c) and (d). The system stabilized at four controllers. sample periods with no overshoot, and the critical point on the Nyquist plot was not encircled, which evidenced that the A. POLE-ZERO-CANCELLATION NON-MINIMUM closed-loop system was stable. REALISATION (PZCNR) APPROACH The tuning polynomial was calculated using the discretized C. POLYNOMIAL (FACTORIZATION/RIPPLE-FREE) zpk from Equation 8 as follows: DEADBEAT CONTROL APPROACH The tuning polynomial was calculated using the discretized mk z−k = 0.0781z−2 , Qz = 1 + z−1 + 0.9219z−2 value of zpk in Equation 8 as M (z) = 0.04955z−1 , C1(z) = 1, As a result, the controller was developed, as shown in and Q(z) = 1 + 0.9505z−1 + 0.3374z−2 + 0.00852z−3 . As Equation 9: a result, the controller was determined using the equations in [7], as shown in Equation 13. The proposed closed-loop pulse 0.2986z4 − 0.07178z3 + 0.02865z2 DBp(z) (9) transfer function is expressed as in Equation 14: z4 + 1.561z3 + 1.497z2 + 0.5315z + 0.01342 The required closed-loop pulse transfer function is pro- 0.1894z4 − 0.04554z3 + 0.01818z2 DBf (z) = (13) vided by: z4 + z3 + 0.9504z2 + 0.3374z + 0.008516 0.04955 (z + 11.81) (z + 0.5335) (z + 0.02728) N(z) = A+ m z −k = 0.0781z−2 1 + 11.81z−1 F(z) = (z) k z5 and presented as in Equation 10: (14) 0.0781(z + 11.81) The step and Nyquist plots of this method are shown in N(z) = (10) z3 Subplots (e) and (f), respectively, in Fig. 4. As can be seen Subplots (a) and (b) in Fig. 4 show the step and Nyquist from the plots, the system stabilized at four sample periods plots, respectively. The closed-loop system settled at two with no overshoot, and the Nyquist plot shows that the crit- sample periods with no overshoot, and on the Nyquist plot, ical point was not encircled, indicating that the closed-loop the critical point was not encircled, demonstrating that the system was stable. closed-loop system was stable. D. POLE PLACEMENT TECHNIQUE (STATE-VARIABLE B. POLE-ZERO-CANCELLATION MINIMUM REALISATION DERIVATION) (PZCMR) APPROACH The pulse transfer function, which was found in Equation 8, Using the discretized zpk from Equation 8, we were able to was transformed into the state space in control canonical form design the tuning polynomial, as shown in the equation below, as: by making use of the formula in [10]:  0 1 0    0 mk z−k = 0.0781z−1 , Q(z) = 1 + 0.9219z−1 A=  0 0 1 B = 0 0.3839 −0.6728 1.241 2 As a result, the controller was successfully obtained, C = 0.2616 1.648 1.78 , D = [0.2616] as shown by Equation 11: 0.2986z4 − 0.07178z3 + 0.02865z2 Let K T denotes the constant required to place the poles at DBp(z) 3 (11) the origin and XC denotes the characteristic polynomial, as in z + 1.483z2 + 0.5315z + 0.01342 Equation 15: The desired closed-loop pulse transfer function may be represented by the following equations: K T = k1 k2 k3 h i N(z) = A+(z) mk z−k = 0.0781z−1 1 + 11.81z−1 Xc = [z ∗ I − A] + B ∗ K T (15) 0.26158 (z + 11.81) (z + 0.5335) (z + 0.02728) −2 Td(z) = z (7) (z − 1) z2 − 0.2404z + 0.09597 0.26158(1 + 11.81z−1 )(1 + 0.5335z−1 )(1 + 0.02728z−1 ) Td (z−1 ) = z−2 (8) (1 − z−1 )(1 − (0.1202 + 0.28552i)z−1 )(1 − (0.1202 − 0.28552i)z−1 ) VOLUME 11, 2023 12449 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation TABLE 2. Summary of simplified controllers, control laws, and their output. A comparison was done between Equation 15 and the The closed-loop pulse transfer function and the deadbeat required polynomial at the origin as a way to obtain matrix controller were constructed using the new closed-loop matri- KT : ces, as indicated in Equations 17 and 18, are shown at the bottom of the page, and the step plot and Nyquist plot are K T = 0.19195 −0.33641 0.62 presented in Fig. 4’s Subplots (g) and (h), respectively. The Equation 16 was used to calculate KW for unity gain: system settled at three sample periods with no overshoot, and on the Nyquist plot, the critical point did not seem to be Kw = 0.18951 encircled, which suggested that the closed-loop system was operating in a stable region. Equation 16 can be used to obtain the overall transfer function by taking into consideration the signal as it travels from the E. HYBRID DEADBEAT CONTROLLER USING STATE-SPACE input to the output [7]: DESIGN Y(z) h i−1 In order to create a deadbeat control that also integrated the = C T [zI − A] + BK T BKW (16) control error, we built a new extended set of state and output E(Z ) matrices using the state matrices from the method discussed Therefore, the closed-loop matrices were developed into in Subsection D, but this time we included an extra variable their final form as: referred to as ν. This construction process was explained  0 0.5 0   0  in [7]. The new substituted matrices were labeled as follows: 0.5  , B =  0  A = 0 0 A 0 à = ; 0 0 0 0.3789 −C T A 1 2.578z5 − 2.004z4 − 0.5606z3 + 0.09092z2 − 0.0974z − 0.004857 DBs(z) = (17) z6 + 12.37z5 + 6.636z4 + 0.1719z3 Y(z) 0.6744 (z + 0.4152) (z + 0.04728) = (18) E(z) z5 12450 VOLUME 11, 2023 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation FIGURE 5. Step and Nyquist plots at (a, b) steady state, (c, d) 40% grid impedance, and (e, f) 80% grid impedance. this is a matrix set of n + 1 by n + 1 where Qc is the controllability matrix. K̃ = 0.1919 −0.3231 0.7828 −0.1895   0 1 0 0  0 0 1 0 à =   0.3839 − 0.6728  Therefore, 1.24 0 K T = 0.1919 −0.6833 1.1275 − 3.0312 1 −0.3231 0.7828   0 Kw = 0.18951 B  1  B̃ = T , B̃ =  2.00  ;  Following the steps outlined earlier, we were able to −C B acquire the deadbeat controller, as in Equation 20, are shown −3.56 at the bottom of the page, and Equation 21 was used to obtain this is a vector set of n + 1 by 1 Equation 22, as shown at the bottom of the page, which describes the closed-loop reference transfer function. K̃ = K T −K W The general feedback transfer function, which goes from h the input to the output, can be found in Equation 23, i 4 K̃ = 0 0 0 1 Q−1 c à (19) and the step plot and the Nyquist plot can be found in 2.579z6 − 2.126z5 − 0.4614z4 + 0.113z3 − 0.1029z2 DBhb = (20) z6 + 13.32z5 + 19.38z4 + 18.59z3 + 9.969z2 + 2.024z + 0.04817 −1 FT = C T zI − G + BK T BKW z (21) 0.67462z (z + 0.4156) (z + 0.04735) FT = (22) (z + 0.2773)(z + 0.05008)(z − 0.0018) VOLUME 11, 2023 12451 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation FIGURE 6. Bode graphs for PZCNRA, PZCMRA, FRA, SVDA, and HBDA at (a) steady state, (b) 40% grid impedance, and (c) 80% grid impedance. FIGURE 7. Schematic representation of proposed method. Y(z) 0.6746(z + 0.4157)(z + 0.02728) Subplots (i) and (j) of Fig. 4, respectively. The system settled = (23) (24) at three sample periods without any overshoot and there was E(Z ) z4 (z − 0.02028) no encirclement of the critical point on the Nyquist plot, both Table 2 summarizes the control laws as well as the out- of which indicated that the closed-loop system was stable. put difference equations for each of the controllers previ- −1 ously addressed. Following that, we discuss which technique Y(z) C T z ∗ I − G + BK T BKW z = (23) is the most stable, especially in terms of grid-impedance E(Z ) −1 (z − 1) C T z ∗ I − G + BK T BK z W variation. 12452 VOLUME 11, 2023 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation FIGURE 8. Current of PZCNRA. FIGURE 9. Voltage of PZCNRA. IV. STABILITY ANALYSIS OF CURRENT CONTROLLERS for each of the five controllers at steady state, as well as At this stage, the stability of the designed controllers was at grid impedances of 40% and 80%. The step plots reveal tested to help the authors to draw a conclusion on which that all of the controllers had either modest or no overshoot, method was the best. Fig. 5 shows the step and Nyquist plots despite the different impedances. In addition, none of the VOLUME 11, 2023 12453 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation FIGURE 10. (a) Id and Iq and (b) output power. FIGURE 11. Current waveforms of single and double sampling and updating. Nyquist plots indicated that the critical point was enclosed, In addition, the currents at the point of common coupling which demonstrated that the closed-loop system continued to (PCC) before and after current injection are depicted in be stable. As demonstrated in Subplots (a), (b), and (c) of Fig. 8’s Subplots (a), (b), and (c), which indicate that there Fig. 6, all of the controllers’ magnitudes were at −20 dB/dec, was negligible distortion when the inverter was hooking to going through 0 dB at ω = 1, which indicated that the poles and dropping from the grid. Subplot (a) in Fig. 9 depicts the of the closed-loop were at the origin. voltage at the PCC in islanded and grid-connected modes, while Subplots (b) and (c) illustrate the distortions that are caused by hooking to and falling from the grid, respec- V. SIMULATION RESULTS tively. Current and voltage deviations were unequivocally To learn more about these sorts of controllers, simulations well within the parameters of what is considered accept- were run for the five controllers, based on the schematic able. Figs. 10(a) and (b) illustrate, respectively, the direct- diagram as shown in Fig. 7. quadrature-zero (dq0) currents of the current controller and 12454 VOLUME 11, 2023 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation FIGURE 12. Current waveforms of single and quadruple sampling and updating. FIGURE 13. Current waveforms of single and decuple sampling and updating. the electricity that was injected into the grid by the inverter. Fig. 11(a) shows the superimposed current waveforms of The graph demonstrates that the 80kW inverter contributed single and double sampling and updating, and it can be around 12 kW of power to the distribution network. observed from the close-up view that about 50 µs of time VOLUME 11, 2023 12455 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation TABLE 3. Summary of I_THD and V_THD at different grid impedances with time-delay compensation. delay was mitigated by adopting double sampling and updat- noticeable difference in its waveform when dropping from ing. Fig. 11(b) shows a comparison of the waveforms of sin- the grid. gle and double sampling and updating, where about 0.9 units Fig. 13(a) shows the superimposed current waveforms of of difference can be observed before and after the transition, single and decuple sampling and updating, where it can and about 5.8 units can be observed during the grid-connected be observed from the close-up view that about 90 µs of mode. From the close-up view, we observed that by using time delay was mitigated by decuple sampling and updat- double sampling and updating, a 50µs time delay in switch- ing, while Fig. 13(b) shows a comparison of the waveforms ing from the off-grid mode to the grid-connected mode was of single and decuple sampling and updating, where about also mitigated. Fig. 12(a) shows the superimposed current 1.6 units of difference can be observed before and after the waveforms of single and quadruple sampling and updating, transition, while about 6.5 units of difference can be seen and it can be observed from the close-up view that about during the grid-connected mode. From the close-up view, 80 µs of time delay was mitigated by quadruple sampling it can be observed also that about 90 µs of time delay in and updating, while Fig. 12(b) shows a comparison of the hooking to the grid was mitigated using the technique of waveforms of single and quadruple sampling and updating, decuple sampling and updating, while there was no notice- where about 1.4 units of difference can be observed before able difference in its waveform when dropping from the and after the transition, while about 6.3 units of difference grid. can be seen during the grid-connected mode. From the close- Fig. 14(a) shows the superimposed current waveforms of up view, it can be observed also that about 80 µs of time single and twenty-fold sampling and updating, where it can delay in hooking to the grid was mitigated using the technique be observed from the close-up view that about 100 µs of time of quadruple sampling and updating, while there was no delay was mitigated by twenty-fold sampling and updating, 12456 VOLUME 11, 2023 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation FIGURE 14. Current waveforms of single and twenty-fold sampling and updating. while Fig. 14(b) shows a comparison of the waveforms of TABLE 4. Summary of I_THD and V_THD at different grid impedance variations without time-delay compensation at fs and fsw of 10 kHz. single and twenty-fold sampling and updating, where about 1.75 units of difference can be observed before and after the transition, while about 6.7 units of difference can be seen during the grid-connected mode. From the close-up view, it can be observed also that about 100 µs of time delay in hooking to the grid was mitigated using the technique of twenty-fold sampling and updating, while there was no noticeable difference in its waveform when dropping from the grid. Table 3 displays the THDs as well as the improvement in time delay accomplished by these controllers. It is evi- dent from the table that there was a significant improvement of 50 µs when double sampling and updating was applied to the PZCNRA. This increase was sustained proportion- ally up to quadruple sampling and updating, and smaller proportional increases were observed with the increase in the number of sampling and updating up to 50-times sam- pling and updating, referred to as the multi-sampling multi- updating approach in this research work. Table 4 displays the THDs of these controllers at the sampling and switching frequencies specified (10 kHz) without taking into account any time delay that may be present in the system. Based on the observation, we concluded that quadruple sampling and updating is the optimal time-delay compensation technique VI. CONCLUSION to be used on micro-controllers, a device that can be easily The digital control of a deadbeat three-phase grid-connected implemented. inverter with time delay for five different controllers was VOLUME 11, 2023 12457 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation designed and evaluated in this paper. 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Power Electron., vol. 32, no. 7, pp. 5023–5034, Jul. 2017, doi: 10.1109/TPEL.2016.2606461. who contributed to the accomplishment of this research work. [18] Q.-C. Zhong, ‘‘Recent results on robust control of time-delay systems,’’ In particular, they would like to thank by communication of in Proc. 7th World Congr. Intell. Control Autom., Chongqing, China, Jun. 2008, pp. 301–306, doi: 10.1109/WCICA.2008.4592941. this research is made possible through monetary assistance [19] D. Pan, X. Ruan, C. Bao, W. Li, and X. Wang, ‘‘Capacitor-current- by Universiti Tun Hussein Onn Malaysia and the UTHM feedback active damping with reduced computation delay for improv- Publisher’s Office via Publication Fund E15216 and by the ing robustness of LCL-type grid-connected inverter,’’ IEEE Trans. Power Electron., vol. 29, no. 7, pp. 3414–3427, Jul. 2014, doi: Advanced Aircraft Engineering Laboratory, National Space 10.1109/TPEL.2013.2279206. Research and Development Agency, Nigeria. In addition, [20] L. Zhou, X. Zhou, Y. Chen, Z. Lv, Z. He, W. Wu, L. Yang, K. Yan, A. Luo, the authors would like to express our gratitude to the group and J. M. Guerrero, ‘‘Inverter-current-feedback resonance-suppression method for LCL-type DG system to reduce resonance-frequency offset members of Advanced Control on Power Converters (ACPC), and grid-inductance effect,’’ IEEE Trans. Ind. Electron., vol. 65, no. 9, FKEE, UTHM. pp. 7036–7048, Sep. 2018, doi: 10.1109/TIE.2018.2795556. 12458 VOLUME 11, 2023 G. Elhassan et al.: Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation [21] C. Zou, B. Liu, S. Duan, and R. Li, ‘‘A feedfoward scheme to improve Research and Development Agency (NASRDA). He is also a Visiting Assis- system stability in grid-connected inverter with LCL filter,’’ in Proc. tant Professor with the Institute of Space Science and Engineering, African IEEE Energy Convers. Congr. Expo., Sep. 2013, pp. 4476–4480, doi: University of Science and Technology, Abuja, Nigeria. His research interests 10.1109/ECCE.2013.6647299. include microwave, antenna, and satellite subsystems designs. [22] M. Lu, X. Wang, P. C. Loh, F. Blaabjerg, and T. Dragicevic, ‘‘Graphical evaluation of time-delay compensation techniques for digitally controlled converters,’’ IEEE Trans. Power Electron., vol. 33, no. 3, pp. 2601–2614, Mar. 2018, doi: 10.1109/TPEL.2017.2691062. [23] A. D. Castro, P. Zumel, O. Garcia, T. Riesgo, and J. Uceda, ‘‘Concurrent ZAINAB YUNUSA (Member, IEEE) received the and simple digital controller of an AC/DC converter with power factor bachelor’s and M.Eng. degrees in electrical engi- correction based on an FPGA,’’ IEEE Trans. Power Electron., vol. 18, no. 1, neering from Bayero University Kano, Nigeria, in pp. 334–343, Jan. 2003, doi: 10.1109/TPEL.2002.807106. 2003 and 2010, respectively, and the Ph.D. degree [24] B.-H. Bae and S.-K. Sul, ‘‘A compensation method for time delay of in sensor technology engineering from Univer- full-digital synchronous frame current regulator of PWM AC drives,’’ siti Putra Malaysia, in 2015. She has published IEEE Trans. Ind. Appl., vol. 39, no. 3, pp. 802–810, May 2003, doi: many local and international journals and confer- 10.1109/TIA.2003.810660. ence proceedings on the design and development [25] Y. Sun, ‘‘The impact of voltage-source-converters control on the power system: The stability analysis of a power electronics dominant grid,’’ of RF and microwave sensors, nanomaterials for Ph.D. thesis, Dept. Elect. Eng., Eindhoven Univ. Tech., Eindhoven, The electronic applications, and the development of Netherlands, 2018. microstrip patch antennas for certain applications. She is currently a Senior [26] L. Zhou, M. Yang, Q. Liu, and K. Guo, ‘‘New control strategy Lecturer with the Department of Electrical Engineering, Bayero University for three-phase grid-connected LCL inverters without a phase-locked Kano, and also an Assistant Professor with the Department of Electrical loop,’’ J. Power Electron., vol. 13, no. 3, pp. 487–496, May 2013, doi: Engineering, University of Hafr Al Batin, Saudi Arabia. She is also a Cor- 10.6113/JPE.2013.13.3.487. porate Member of the Nigerian Society of Engineers and has been a member [27] Y. Tang, P. C. Loh, P. Wang, F. H. Choo, F. Gao, and F. Blaabjerg, ‘‘Gener- of the Council for the Regulation of Engineering of Nigeria, since 2011. alized design of high performance shunt active power filter with output Her research interests include RF and microwave devices and applications, LCL filter,’’ IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1443–1452, nanomaterials for electronic applications, gas sensors, antenna design and Mar. 2012, doi: 10.1109/TIE.2011.2167117. [28] A. Reznik, M. G. Simões, A. Al-Durra, and S. M. Muyeen, ‘‘LCL filter applications. She is also a MNSE and a COREN. design and performance analysis for grid-interconnected systems,’’ IEEE Trans. Ind. Appl., vol. 50, no. 2, pp. 1225–1232, Mar. 2014. GARBA ELHASSAN was born in Gombe, Nigeria, MOHAMMED AHMED was born in Misau, in 1985. He received the B.Eng. degree (Hons.) Bauchi, Nigeria. He received the Ph.D. degree in in electrical and electronics engineering from the electrical engineering from Universiti Tun Hus- Federal University of Technology, Yola, Nigeria, sein Onn Malaysia (UTHM). He attended the Fed- in 2011, and the Master of Engineering degree eral Polytechnic Staff School Bauchi, Government from Bayero University Kano, Nigeria, in 2017. Science Secondary School Toro in Bauchi State, He is currently pursuing the Ph.D. degree with Abubakar Tafawa Balewa University (ATBU), Universiti Tun Hussein Onn Malaysia. Since 2013, Bauchi, Nigeria, where he is currently working as he has been a Staff of the National Space Research the Academic Staff of the Department of Electrical and Development Agency, Nigeria. His current and Electronics Engineering. research interests include robust deadbeat control system on power elec- tronics applications and DC/DC converter topologies for grid-connected applications. MUBASHIR HAYAT KHAN was born in Bagh, SHAMSUL AIZAM ZULKIFLI was born in Azad Jammu and Kashmir (AJ&K), Pakistan. Kajang, Selangor, Malaysia. He received the B.S. He received the B.Sc. (Hons.) and M.S. degrees and M.Sc. degrees from Universiti Putra Malaysia from the Mirpur University of Science & Tech- (UPM), in 2003 and 2006, respectively, and nology, AJ&K, in 2008 and 2012, respectively. the Ph.D. degree in control system engineering From 2008 to 2014, he was associated with from Loughborough University, U.K., in 2012. Huawei Technologies (Pvt.) Ltd., Hydro-Electric He is currently an Associate Professor with the Board of AJ&K, NESPAK (Pvt.) Ltd., and PEL Department of Electrical Power Engineering, Fac- (Pvt.) Ltd. In 2014, he joined the University of ulty of Electrical and Electronic Engineering, Poonch Rawalakot (UPR) as a Lecturer with the Universiti Tun Hussein Onn Malaysia (UTHM). Faculty of Engineering and Technology, Department of Electrical Engineer- His research interests include robust control system on power elec- ing. Since 2019, he has been working as a Ph.D. Research Scholar at the tronics application, parallel inverter application, and smart grid topol- Faculty of Electrical Engineering, University Tun Hussein Onn Malaysia. ogy for inverter-grid connection. For more information visit the link His research interest includes inverter-based smart grid control. (https://sites.google.com/site/acul1508/). SOLOMON ZAKWOI ILIYA (Member, IEEE) received the Ph.D. degree from the Wireless Com- munication Center (WCC), Universiti Teknologi RONALD JACKSON was born in Sarawak, Malaysia (UTM), Johor Bahru, Johor, Malaysia. Malaysia, in 1991. He received the B.Eng. (Hons.) He attended the Beijing Institute of Tracking and M.Sc. degrees in electrical engineering from and Telecommunications Technology (BITTT), Universiti Tun Hussein Onn Malaysia, Johor, Beijing, China, and the Federal University of Tech- Malaysia, in 2017 and 2019, respectively, where he nology Minna, Minna, Nigeria, for postgraduate is currently pursuing the Ph.D. degree. His current and undergraduate studies, respectively. He has research interests include microgrid control, power over 20 years of experience in his field of study. flow control, self-synchronization, and smart grid Currently, he is the Deputy Director Engineer of the Center for Satellite application. Technology Development (CSTD), an activity arm of the National Space VOLUME 11, 2023 12459