(PDF) Low-voltage 2D materials-based printed field-effect transistors for integrated digital and analog electronics on paper

ARTICLE https://doi.org/10.1038/s41467-020-17297-z OPEN Low-voltage 2D materials-based printed field-effect transistors for integrated digital and analog electronics on paper Silvia Conti 1,7, Lorenzo Pimpolari1,7, Gabriele Calabrese 1, Robyn Worsley2, Subimal Majee2, Dmitry K. Polyushkin3, Matthias Paur3, Simona Pace 4,5, Dong Hoon Keum4,5, Filippo Fabbri4,6, Giuseppe Iannaccone1, Massimo Macucci1, Camilla Coletti 4,5, Thomas Mueller3, Cinzia Casiraghi2 & Gianluca Fiori1 ✉ 1234567890():,; Paper is the ideal substrate for the development of flexible and environmentally sustainable ubiquitous electronic systems, which, combined with two-dimensional materials, could be exploited in many Internet-of-Things applications, ranging from wearable electronics to smart packaging. Here we report high-performance MoS2 field-effect transistors on paper fabri- cated with a “channel array” approach, combining the advantages of two large-area techni- ques: chemical vapor deposition and inkjet-printing. The first allows the pre-deposition of a pattern of MoS2; the second, the printing of dielectric layers, contacts, and connections to complete transistors and circuits fabrication. Average ION/IOFF of 8 × 103 (up to 5 × 104) and mobility of 5.5 cm2 V−1 s−1 (up to 26 cm2 V−1 s−1) are obtained. Fully functional integrated circuits of digital and analog building blocks, such as logic gates and current mirrors, are demonstrated, highlighting the potential of this approach for ubiquitous electronics on paper. 1 Dipartimento di Ingegneria dell’Informazione, University of Pisa, Pisa 56122, Italy. 2 Department of Chemistry, University of Manchester, Manchester M13 9PL, UK. 3 Institute of Photonics, Vienna University of Technology, Vienna 1040, Austria. 4 Center for Nanotechnology Innovation @NEST, Istituto Italiano di Tecnologia, Pisa 56127, Italy. 5 Graphene Labs, Istituto Italiano di Tecnologia, Genova 16163, Italy. 6 CNR, Scuola Normale Superiore, Pisa 56127, Italy. 7These authors contributed equally: Silvia Conti, Lorenzo Pimpolari. ✉email: gianluca.fi

NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications 1 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-17297-z I n recent years, electronics has witnessed impressive techno- fabrication processes, their combination could open a possible logical achievements, owing to the development of new pro- exploitation at the industrial level. cesses and materials with extraordinary electrical and The MoS2 FETs fabricated with the channel array method operate mechanical properties, which have enabled the development of at supply voltage below 2 V, with remarkable transistor performance, Internet of Things applications, ranging from wearable electro- such as an average field-effect mobility of 5.5 cm2 V−1 s−1 (with best nics to mobile healthcare. This has led to a continuous and performance reaching 26 cm2 V−1 s−1), negligible leakage currents marked increase in demand of light-weight, flexible, and low-cost (smaller than 5 nA), and an average ION/IOFF ratio of 8 × 103 (up to devices, posing strong constrains on traditional fabrication 5 × 104). We further exploit the possibility to produce high- methods1,2. In addition, this type of pervasive and versatile performance transistors with the channel array method by demon- electronics had led to further concerns on sustainability, such as strating more complex circuits, such as logic gates (such as NOT and the treatment of waste at the end of the product life-cycle. NAND) and analog circuits. This paves the way towards the intro- Derived from abundant and renewable raw materials, paper- duction of the channel array approach in all applications where based consumer electronics is expected to alleviate landfill and flexible and/or disposable electronics is required. environmental problems and to reduce the impact associated with recycling operations, whilst offering cost-effectiveness and large flexibility3. Despite the fact that several devices and applications Results have been reported in the literature4, paper is still a challenging Fabrication of MoS2 FETs on paper. The rationale of our substrate for electronics, rarely employed without the addition of approach is the combination of two fabrication techniques, which coating/laminating layers5,6. Its porous structure (which in turn up to now have been used for very different applications, to have leads to high roughness), limited stability and durability (mainly high-quality semiconducting substrates easily customizable to due poor thermal and humidity resistance), and high hygro- obtain devices and circuits with a versatile printing technique. scopicity (which can influence the electrical characterization of The advantage of inkjet-printing is the fast prototyping, which devices fabricated on top of it), combined with the lack of win- allows for on-the-fly corrections as well as easy pattern changes, ning reliable fabrication techniques, is preventing its exploitation simplifying the manufacturing process. Moreover, being an at the industrial level7,8. additive and mask-less method, it also cuts down materials and Two-dimensional materials (2DMs) combine good tunable elec- energy consumption, reducing the number of processing steps, tronic properties with high mechanical flexibility, making them time, space, and waste production during the fabrication. On the extremely promising as building blocks for flexible electronics9,10. other hand, inkjet-printing presents critical aspects, such as the Moreover, they can be easily produced in solution with mass scalable need to use inks with specific rheological properties, and, more and low-cost techniques, such as liquid-phase exfoliation11, enabling importantly, the current lack of semiconducting 2DM-based inks their deposition by simple fabrication techniques such as inkjet for high-performance FETs. Even if expensive, lacking in com- printing12–17. 2D semiconducting materials, such as transition metal patibility with arbitrary substrates, suffering from atomic vacan- dichalcogenides (TMDCs)18,19, with extended bandgap tunability cies and batch-to-batch variations, CVD is, so far, the most- through composition, thickness, and possibly even strain control, promising bottom–up approach to obtain high-quality semi- represent promising materials as channels for field-effect transistors conducting layer and may become the method of choice, also (FETs), which are fundamental components in electronics. However, considering the recent progress in the CVD growth of MoS2 up to now, fully printed TMDC-based transistors have demonstrated involving a low-cost, large-area roll-to-roll approach31. limited performance, showing mobility of the order of under Figure 1a illustrates the procedure followed to pattern CVD 0.5 cm2 V−1 s−1 and ION/IOFF ratios of hundreds, using liquid elec- MoS2 and its transfer to paper substrate (a detailed description of trolytes as insulating layers20,21. Among the various TMDCs, the process is reported in Methods, an alternative method for molybdenum disulfide (MoS2) has been widely studied, owing to its CVD growth and transfer is presented in Supplementary Note 1). outstanding electrical and optical properties22–26. Lin et al. 27 After the transfer, the polystyrene carrier film is dissolved in reported FETs made with solution-processed MoS2, showing toluene, resulting in MoS2 strips on paper, as shown in Fig. 1b (an remarkable performance (average mobility of ~7–11 cm2 V−1 s−1), atomic force microscopy micrograph of the MoS2 film on the but device fabrication required acid cleaning and annealing above sapphire substrate before the transfer is reported in Supplemen- 200 °C, which are incompatible with substrates such as paper. A large tary Note 2). mobility of 19 cm2 V−1 s−1 for a MoS2/graphene transistor was To evaluate the crystalline quality of the MoS2 before and after reported in ref. 28: graphene allows increasing carrier mobility, but the transfer process from the rigid substrate to the paper, Raman this negatively affects the ION/IOFF ratio. spectroscopy is employed. Figure 1c shows the Raman spectra We combine chemical vapor deposition (CVD), for the growth before (red line) and after (cyan line) the transfer. The red of high-quality MoS2 channels, with inkjet printing29,30, which spectrum presents the E2g and A1g modes at 383 cm−1 and at allows to design and fabricate customizable devices and circuits 403 cm−1 of single-layer MoS2, representative of the in-plane and exploiting 2DMs-based inks, whose capability to be printed on out-of-plane vibrations of S–Mo–S, respectively32. After the top of CVD-grown materials has been successfully demonstrated transfer process, the MoS2 Raman modes appear slightly shifted in ref. 16. In this work, an application-specific integrated circuit and broadened, i.e., the E2g and A1g modes peak at 380 cm−1 and design approach, known as “channel array”, is proposed: this is at 400 cm−1, respectively. As previously reported in ref. 33, the based on the transfer of strips of CVD-grown MoS2, onto paper softening of Raman modes can be attributed to uniaxial strain, substrate where the rest of the devices and circuits, source and albeit the E2g mode should suffer a larger shift compared with the drain contacts (which define the effective channel length and A1g mode. In our case, the softening of the Raman modes is width), gate dielectric, gate contacts, and connections, are fully comparable, ruling out any strain effect on the MoS2. Therefore, customized exploiting inkjet printing technique, giving a degree we argue that the softening is mainly owing to heating effects of freedom to the designer. This method allows to keep the related to the poor heat dissipation of the paper substrate. This flexibility and versatility of an all-inkjet technology, with the hypothesis is also supported by the broadening of the full-width- difference that here a high-quality channel is already placed on at-half-maximum (FWHM) of both modes. Indeed, the E2g the substrate, by taking advantage of the CVD-grown TMDC. FWHM increases from ~3 cm−1, before transfer, up to ~7 cm−1 Moreover, as both methods are compatible with large-area after the transfer process. In the case of the A1g mode, the 2 NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-17297-z ARTICLE a CVD MoS2 MoS2 pattern Polystyrene on sapphire on sapphire Spin coating of Ar/SF6 plasma polystyrene for etching transfer Sapphire Immersion in KOH/DI water solution MoS2 pattern Transfer on paper on paper Toluene treatment Paper b c Before transfer After transfer A1g E2g Strips of Intensity (arb. un.) transferred CVD MoS2 Paper 300 350 400 450 500 550 600 Raman shift (cm–1) d MoS2 Silver g Inkjet-printed hBN Inkjet-printed eletrodes dielectric e hBN f Transferred CVD MoS2 Silver Paper Fig. 1 Transferring scheme of MoS2 channel stripes and fabrication process of MoS2 FETs. a Schematic representation of the patterning and transferring procedure employed to obtain MoS2 strips on paper. b Optical micrograph showing the transferred MoS2 strips on paper. The scale bar corresponds to 1 mm. c Raman spectra acquired on the as-grown MoS2 layer on rigid substrate (red line) and after MoS2 transfer to paper (cyan line). d–f Fabrication steps of the inkjet-printed transistors on paper: d Inkjet-printing of silver source and drain contacts. e Inkjet-printing of the hBN dielectric layer (defined by the blue-dotted frame). f Inkjet printing of silver top-gate contact. The scale bars in d–f correspond to 250 μm. g Sketch showing an inkjet-printed circuit on paper with CVD-grown MoS2 channel. broadening is less evident, with the FWHM increasing from routes defined between the MoS2 strips, to create the integrated ~4 cm−1 up to ~6 cm−1. circuit in an efficient and versatile way. This approach is Figure 1d–f show the fabrication of inkjet-printed MoS2 FETs qualitatively described in Fig. 1g. on paper. First, the source and drain contacts are printed on a MoS2 stripe to define the channel area of the transistor (Fig. 1d). Electrical characterization of MoS2 FETs. At first, a commercial Second, a hexagonal boron nitride (hBN) film is printed on the silver ink (see Methods) was chosen to print the electrodes, MoS2 channel (Fig. 1e). This 2D insulating material is chosen because it can assure very high conductivity with just one printing because of its notable dielectric properties and negligible leakage pass, and it has shown ohmic contact with MoS229. Typical current15,20,34,35. Finally, a top-gate electrode is printed on top of transfer and output characteristics of the MoS2 FETs are reported hBN (Fig. 1f). Either silver or graphene inks have been used to in Fig. 2a, c. The devices work in the enhancement mode, can print the source and drain contacts as well as the top-gate operate at low supply voltage (<2 V), and exhibit a threshold contacts. The FETs are then connected to each other using the voltage (VTH) in the range of ±1 V (see Supplementary Fig. 7c and NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications 3 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-17297-z a Drain voltage = 2.0 V b Drain voltage = 2.0 V 3.0 10–6 10–7 Drain current (µA) 2.0 Current (A) 10–8 10–9 IIDSI IIGSI 1.0 –10 10 10–11 0.0 10–12 –0.5 0.0 0.5 1.0 1.5 2.0 –0.5 0.0 0.5 1.0 1.5 2.0 Gate voltage (V) Gate voltage (V) c 5.0 d VG = 0.0 V VG = 0.25 V 10–6 4.0 VG = 0.50 V VG = 0.75 V Drain current (µA) Drain current (A) VG = 1.00 V 3.0 VG = 1.25 V 10–7 VG = 1.50 V VG = 1.75 V 2.0 10–8 1.0 10–9 0.0 ID VDY 10–10 0.0 0.5 1.0 1.5 2.0 0.01 0.1 1 Drain voltage (V) Drain voltage (V) e 102 f Unbent Field-effect mobility (cm2 V–1 s–1) Best, this work 55 10–6 R = 32 mm 51 R = 20 mm 101 43 28 Average, this work 53 25 10–7 R = 12 mm Drain current (A) R = 8 mm 57 54 56 44 10–8 Back to unbent 100 Graphene 46 49 contacts, IGS this work 10–9 50 10–1 47 10–10 48 52 10–11 10–2 10–12 44 10–3 10–13 10–1 100 101 102 103 104 105 106 107 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 (ION/IOFF)/VDD Gate voltage (V) Fig. 2 Electrical characterization of the MoS2 FETs with inkjet-printed silver contacts in ambient conditions. a Typical transfer characteristic curve measured as a function of the gate voltage for a drain voltage of 2.0 V. Logarithmic scale: black dots, drain current; red dots, gate current. b Typical transfer characteristic curve measured as a function of the gate voltage for a drain voltage of 2.0 V in linear scale. c Typical output characteristic measured at different gate voltages (from VGS = 0.0 V to VGS = 1.75 V, steps of 0.25 V). d Log–log curves of the output characteristic in low drain voltage region. Ohmic behavior is observed, suggesting good electrical contact between the silver contacts and MoS2. e Field-effect mobility and (ION/IOFF)/VDD for FETs characterized on paper substrates previously reported in the literature. VDD is the supply voltage for each device. Blue stars, this work, inkjet-printed silver contacts; purple star, this work, inkjet-printed graphene contacts; black dots, 2D materials (25, 28, 43); red dots, organic semiconductors (44, 45, 46, 47, 48, 49, 50); yellow dots, inorganic oxides (51, 52, 53, 54, 55); green dots, CNTs (56, 57). f Transfer characteristics and gate leakage currents measured for different bending radii along the current direction for a drain voltage of 2 V; inset, picture of a sample with MoS2 FET fabricated on paper. Supplementary Fig. 7e). As can be seen, the leakage current IGS Charge carrier field-effect mobility (µFE) is one of the most (red dots, Fig. 2a) through the insulator is negligible as compared important figures of merit defining the quality of transistor to the drain current IDS (black dots, logarithmic scale, Fig. 2a; electrical performance. It can be extrapolated using the classical black dots, linear scale, Fig. 2b), further confirming the good model for devices operating in the saturation regime (VDS > insulating properties of the inkjet-printed hBN film. The VGS − VTH): saturation regime is reached for low drain-to-source voltage pffiffiffiffiffiffi2 L 1 ∂ IDS (VDS), i.e., VDS < 2 V. Almost negligible contact resistance is μFE ¼ 2 ð1Þ shown from the output characteristic. Indeed, as can be seen from W Ci ∂VGS the log–log plot (Fig. 2d), the linearity parameter γ, describing the where Ci is the capacitance of the insulator per unit area, W and L γ relation IDS / VDS , is found to be 1.1 on average, indicating a are the transistor channel width and length, respectively, and VGS is good contact between the CVD MoS2 and the inkjet-printed silver the gate voltage. As suggested in ref. 8, in order to avoid any electrodes. mobility overestimation, the capacitance was measured under 4 NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-17297-z ARTICLE quasi-static conditions (details about the quasi-static capacitance fabrication techniques for the deposition of insulator and contact measurement and setup are reported in Supplementary Note 3). layers, as well. It is worth mentioning, that the mobility extracted To this purpose, parallel plate capacitor structures, in which in this work is comparable to the one found for CVD MoS2 FETs hBN is sandwiched between silver bottom/top electrodes were entirely fabricated using conventional microelectronic techniques fabricated and tested (see Methods). The extracted average value of on planarized paper substrates25. Note that the type of paper used 230 nF cm2 is in line with other quasi-static measurement in the literature may be different, and this may affect the performed on both organic and hybrid materials8,36–38. Thanks performance of the devices and the reproducibility, hence to the high capacitive coupling, which results in an enhanced comparison should be done carefully. In some cases, planarization polarization and leads to a high number of carriers at the insulator- layers were introduced to mitigate the surface roughness of the semiconductor interface, the devices show an average charge carrier paper substrates and high-temperature processes were employed, mobility of 5.5 cm2 V−1 s−1 and ION/IOFF ratio of 8 × 103. ION is thus increasing the complexity of the transistor manufacturing. In computed for IDS extracted for gate voltage VGS = VGSoff + VDD and our work, the fabrication process and the electrical characteriza- drain voltage VDS = VDD, where VDD is the supply voltage, and tion are carried out at ambient condition on a commercially VGSoff is the gate voltage for the lowest current flowing in the device, available paper, designed for printed electronics (see Supplemen- i.e., the OFF current IOFF39. The detailed electrical characterization tary Note 6) that cannot withstand temperatures over 120 °C. The is reported in Supplementary Figs. 2 and 3. Remarkably, this potentiality of our approach stands in the coherent combination of mobility value is comparable to already reported CVD-grown MoS2 two large-area fabrication processes in order to obtain good transistors fabricated on rigid substrates using standard microelec- electrical performances. In Supplementary Note 5 and Supple- tronic fabrication techniques40–42, confirming that our methodol- mentary Data 2, a comparison with devices fabricated on flexible ogy, based on the channel array, allows to use inkjet-printing for the substrates (other than paper) is reported. As can be seen, our fabrication of the devices, without affecting the electronic properties devices are comparable with the best-in-class presented devices. of the channel. In order to confirm the compatibility of our technology with Figure 2e shows µFE and the normalized ION/IOFF ratio for our flexible substrates, the electromechanical properties of the devices devices compared with those previously reported in the literature: are investigated for various bending radii (R) (more details can be the closer the points to the top-right corner, the better the found in Supplementary Note 4.1). Figure 2f shows transfer performance. We considered only transistors fully fabricated on characteristics recorded for R values of 32, 20, 12, and 8 mm. No paper or transferred on paper after fabrication. For a fair relevant changes both in the drain and the gate currents are comparison, all the ION/IOFF values are re-calculated considering observed, indicating that the device electrical performance is not the International Technology Roadmap for Semiconductors affected under the applied strain conditions. definition39, and then divided by the respective supply voltage We have then focused on the fabrication of fully 2D-material- VDD. This normalization allows to take into account the operating based transistors with inkjet-printed graphene source, drain, and voltage ranges of the considered FETs, which is a crucial problem gate contacts (see Methods). An optical micrograph of a fully 2D- for portable applications, where low power consumption is often material-based FET is shown in Fig. 3a, whereas Fig. 3b, c report required. They have been divided into four groups according to typical transfer and output characteristic, respectively. These the nature of the semiconductor used as channel: 2D transistors show a reduced effective μFE (~0.8 cm2 V−1 s−1), and materials25,28,43 organic semiconductors44–50, inorganic oxide an ION/IOFF ratio about one order of magnitude smaller (~3 × semiconductors51–55, carbon nanotubes56,57. Our devices show 103), compared with transistors with silver contacts (Fig. 2e). The competitive electrical performance and are the only one, where reduced performance is likely related to the formation of Schottky both the contacts and the insulating layers are deposited by means contacts, which in turn increases the contact resistance, as evident of inkjet printing (for a detailed comparison see Supplementary from Fig. 3c, where non-linear behavior of the output Data 1). While maintaining a high ION/IOFF ratio, the mobility characteristic can be observed for small VDS. However, it is values extracted from the MoS2 FETs are larger than those remarkable that the extracted field-effect mobility is only six obtained for organic semiconductors. Transistors that show times smaller than the one obtained for a thin film transistor with comparable or better performance than those presented in this exfoliated MoS2 channel and CVD‐grown graphene source/drain work, as reported in refs. 25,51,53,55, were fabricated using micro- electrodes (4.5 cm2 V−1 s−1)58. a b Drain voltage = 2.5 V c 2.0 VDS = 2.5 V VGS = 0.0 V –6 1.0 10 IDS (µA) 1.0 VGS = 0.25 V 0.0 VGS = 0.50 V 10–7 0.8 Drain current (µA) MoS2 Graphene 0.0 1.0 2.0 VGS = 0.75 V hBM VGS (V) Current (A) VGS = 1.00 V 10–8 0.6 VGS = 1.25 V IDS VGS = 1.50 V 10–9 IGS 0.4 VGS = 1.75 V 10–10 Graphene 0.2 10–11 0.0 10–12 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 Gate voltage (V) Drain voltage (V) Fig. 3 Optical image and electrical characterization of a fully 2D-material-based FETs. a Optical micrograph of a fully 2D-material-based transistor on paper. The scale bar corresponds to 250 μm. b Typical transfer characteristic curve measured as a function of the gate voltage for a drain voltage of 2.5 V. Logarithmic scale: black dots, drain current; red dots, gate current. inset, Typical transfer characteristic curve measured as a function of the gate voltage for a drain voltage of 2.5 V in linear scale. c Typical output characteristic curves measured at increasing gate voltages (from VGS = 0.0 V to VGS = 1.75 V, steps of 0.25 V). NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications 5 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-17297-z a VDD b c 30 VDD R 5 25 Output voltage (V) 4 R 20 3 Gain 15 VOUT 2 10 VOUT 5 VIN M 1 VIN 0 0 MoS2 0.0 1.0 2.0 3.0 4.0 5.0 GND Input voltage (V) d e R f VDD VDD 5 M1 Output voltage (V) VOUT 4 R VIN1 VOUT 3 VIN1 M1 2 1 VIN2 M2 M2 0 VIN2 (0, 0) (0, 1) (1, 0) (1, 1) Input state GND MoS2 g h i M2 40.0 B IREF = 1.5 µA IREF A Output Current (µA) B IREF = 3 µA 30.0 A IOUT 20.0 + M1 M2 VOUT M1 – GND 10.0 0.0 MoS2 0.0 2.0 4.0 6.0 8.0 Output voltage (V) Fig. 4 Logic gates and current mirror based on inkjet-printed MoS2 FETs. a Electrical schematic and b optical image of an inverter. c Output voltage (left axis) and voltage gain (right axis) of the inverter gate as a function of the input voltage. d Electrical schematic and e optical image of a NAND gate. f Output voltage of the NAND gate as a function of the input states (VIN1, VIN2). Voltage bias is 5 V for both the inverter and the NAND gate. g Electrical schematic and h optical image of a current mirror. i Output current of the current mirror as a function of the output voltage for two different values of the reference current. Legend: VDD, supply voltage; GDN, ground reference; VIN and VOUT, input and output voltage; M, inkjet-printed transistor. R, inkjet-printed graphene resistor. The scale bars in b, e, h correspond to 250 μm. Integrated circuits on paper. To demonstrate the potential of The inverter exhibits a high-gain value, close to 30 under a the fabricated FETs as building blocks for integrated circuits voltage bias of 5 V, in agreement with previously reported exploiting the channel array technology, different types of cir- inverters based on CVD-grown MoS2 fabricated on rigid cuits have been designed and fabricated. MoS2 FETs with substrates41,59. inkjet-printed silver contacts were selected owing to the high The schematic and the optical image of a NAND gate are ION/IOFF ratio, intrinsic gain, and low power supply voltage to shown in Fig. 4d, e, whereas Fig. 4f shows the output voltage of fabricate a resistor-transistor logic (RTL) inverter, consisting of the circuit as a function of the inputs (VIN1,VIN2). The low and a transistor and an inkjet-printed graphene resistor. Figure 4a, b high logic values of the inputs correspond to voltages of 0 V and show the schematic and the optical image of a RTL inverter, 5 V, respectively. The output voltage is high (i.e., at logic state “1”) respectively. The transfer characteristic of an inverter is shown when at least one input is in the logic state “0”, and therefore at in Fig. 4c (left axis), together with the gain G (right axis), least one transistor is in the OFF state. The output voltage is low defined as the slope dVOUT/dVIN of the transfer curve (where (i.e., at logic state “0”) only when both inputs are at the logic state VIN and VOUT are the input and output voltages, respectively). “1”: in these conditions both transistors are in the ON state. The 6 NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-17297-z ARTICLE possibility to implement NAND gates is particularly important, as structure on the growth substrate. The pattern is defined by means of Ar/SF6 all other logic functions can be implemented using NAND gates. plasma etching in an Oxford Cobra Reactive Ion Etching system. The etch mask is created by optical lithography using AZ 5214E photoresist. A 5% KOH solution in As a further demonstration of the potential of the presented DI water is employed to remove the etch mask. The sample is then rinsed in DI technology, we propose an application for analog electronics. water for several times to remove the KOH remnants. To transfer the patterned Current mirrors are fundamental building blocks in analog film, the sapphire substrate with the MoS2 layer film is first covered with a poly- electronic circuits, where they are widely used for operational styrene film by spin coating a solution of polystyrene in toluene onto the substrate, amplifiers, bandgap voltage reference, etc.60, and they can also be which is then immersed in DI water. To facilitate the lift-off process, a solution of KOH in DI water is also added for a short time. After that, the carrier polystyrene exploited in neural networks, in order to implement matrix-vector film with the MoS2 layer is rinsed for several times in DI water. To remove the multiplication61. Figure 4g, h show the schematic and the optical absorbed water the polymeric film is dried at 50 °C in dry air atmosphere and then image of the fabricated current mirror. The output transistor (M2) is transferred onto the paper substrate. To improve the adhesion between the carrier 10 times wider than the input transistor (M1), whereas all the other polymer film and the wafer the sample is baked at 150 °C for about an hour. The polystyrene carrier film is then dissolved in toluene resulting in a MoS2 film on transistor parameters are identical; therefore, the current mirror has paper. Raman characterization before and after transfer has been performed with a a nominal gain of 10. Figure 4i shows the current mirror output Renishaw InVia spectrometer equipped with a confocal optical microscope and a characteristic, i.e., the output current as a function of the output 532 nm excitation laser. The spectral resolution of the system is 1 cm−1. Raman voltage, for two different values of the input reference current. As experiments were carried out employing a ×50 objective (N.A. 0.6), laser power of 5 mW and an acquisition time of 2 s. The pixel size is 1 µm × 1 µm. shown in the plot, for sufficiently high output voltages (i.e., M2 in saturation) the output current is about 10 times larger than the Devices fabrication. MoS2 transistors are fabricated in a top-gate/top-contact reference current (IREF), in accordance with the circuit design. configuration on the CVD MoS2 stripes transferred on paper. A Dimatix Materials Printer 2850 (Fujifilm) is used to define the contacts and the insulator layers under Discussion ambient conditions. It is worth underlining that no annealing or post-treatment process is performed after any printing step. The silver ink is deposited with a We have successfully demonstrated high-performance MoS2- single printing pass using one nozzle, a drop spacing of 40 μm, and keeping the based transistors that combine the numerous advantages of using printer platen at room temperature. Cartridges with a typical droplet volume of 1 pL paper as a substrate with the versatility of inkjet-printing tech- are used for the definition of the contacts. When the 2.5 mg ml−1 graphene ink is nique, whilst maintaining the good electrical properties of CVD- employed, source and drain contacts are inkjet-printed using a drop spacing of 20 μm, grown MoS2. A maximum field-effect mobility of 26 cm2 V−1 s−1 and 20 printing passes. Cartridges with a droplet volume of 10 pL are used for the definition of the graphene contacts. For the top-gate contacts, only six printing passes and an ION/IOFF ratio of up to 5 × 104 were achieved. Bending of graphene ink at the same concentration are used in order to reduce the possibility tests have shown that the device electrical properties are robust of overlapping with the source and drain contacts (which would significantly increase under applied strain (up to a bending radius of 8 mm). Moreover, the leakage current) at each print pass. A ~2 mg/mL hBN ink is printed on top of the our device fabrication approach has been proven to be suitable for CVD-grown MoS2 using a drop spacing of 20 μm and 80 printing passes. Cartridges with a droplet volume of 10 pL are used for the definition of the insulating layer. the development of complete integrated circuits, such as high- Several transistors have been fabricated (with a yield of around 80%) and char- gain inverters, logic gates, and current mirrors. This work acterized with a nominal width of ~500 μm and length varying between 40 μm and demonstrates the great potential of the channel array technology 60 μm (further details can be found Supplementary Table 1). for next-generation electronics on paper, ranging from analogic Parallel plate capacitors with silver/graphene bottom/top electrodes are also printed on paper to evaluate the capacitance of the hBN layers. The inks and the to digital circuits for cost-efficient and practical applications. fabrication procedures are kept the same for all the reported devices. Methods Electrical characterization. All the electrical measurements are performed under Materials. PEL P60 (purchased from Printed Electronics Limited) is used as paper ambient conditions. The transistor characterization is carried out using a Keithley substrate (more details can be found in Supplementary Note 6). A commercial SCS4200 parameter analyzer. Capacitance measurements are performed with an silver ink (Sigma-Aldrich) is used to print the metal contacts. Bulk graphite R&SRTO2014 oscilloscope and a HP 33120A function/arbitrary waveform gen- (purchased from Graphexel or Sigma-Aldrich, 99.5% grade) and bulk boron nitride erator. The detailed description of the measurement setup can be found in (purchased from Sigma-Aldrich, >1 μm, 98% grade) powders were used to prepare the Supplementary Information. the 2DMs inks. The bulk powders are dispersed in deionized water (resistivity 18.2 MΩ cm−1) at a concentration of 3 mg mL−1 and 1-pyrenesulphonic acid sodium salt (PS1, purchased from Sigma-Aldrich), purity ≥97%, is added at a Data availability concentration of 1 mg mL−1. The graphite and boron nitride dispersions are then The data that support the findings of this work are available from the corresponding sonicated for 72 h and 120 h, respectively, using a 300 W Hilsonic HS 1900/Hil- authors upon reasonable request. sonic FMG 600 bath sonicator at 20 °C. The resultant dispersions is centrifuged at 3500 rpm (g factor = 903) for 20 minutes at 20 °C using a Sigma 1–14 K refri- Received: 12 November 2019; Accepted: 18 June 2020; gerated centrifuge in order to separate out and discard the residual bulk, non- exfoliated flakes. The remaining supernatant, now containing the correct flake size and monolayer percentage, is centrifuged twice to remove excess PS1 from the dispersion. After washing, the precipitate is re-dispersed in the printing solvent, made as described in ref. 16. The concentration of the resultant inks are assessed using a Varian Cary 5000 UV-Vis spectrometer and the Lambert-Beer law, with extinction coefficients of 2460 (at 660 nm) and 1000 L g−1 m−1 (at 550 nm) for References graphene11 and hBN62, respectively. Full characterization of the material (lateral 1. Huang, S., Liu, Y., Zhao, Y., Ren, Z. & Guo, C. F. Flexible electronics: size and thickness distribution, crystallinity, etc.) has been presented in refs. 16,34,63. stretchable electrodes and their future. Adv. Funct. Mater. 29, 1805924 (2019). 2. Wang, C. et al. Advanced carbon for flexible and wearable electronics. Adv. Growth of MoS2 and transfer on paper. Single- and few-layer MoS2 have been Mater. 31, 1801072 (2019). grown by CVD on c-plane sapphire64. CVD growth is performed at atmospheric 3. Tobjörk, D. & Österbacka, R. Paper electronics. Adv. Mater. 23, 1935–1961 pressure using ultra-high-purity Ar as the carrier gas. The substrates are placed (2011). face-down 15 mm above a crucible containing ∼3 mg of MoO3 (99.998% Alfa 4. Ha, D., Fang, Z. & Zhitenev, N. B. Paper in electronic and optoelectronic Aesar) and loaded into a split-tube two-zone CVD furnace with a 30 mm outer devices. Adv. Electron. Mater. 4, 1–20 (2018). diameter quartz tube. A second crucible containing 1 g of sulfur (99.9% purity, 5. Lessing, J. et al. Inkjet printing of conductive inks with high lateral resolution Sigma-Aldrich) is loaded upstream from the growth substrates and heated to 140 ° on omniphobic ‘rF paper’ for paper-based electronics and MEMS. Adv. Mater. C. Just before starting the growth, the tube is flushed with Ar at room temperature 26, 4677–4682 (2014). and atmospheric pressure. The furnace is pre-heated to 750 °C for few hours for 6. Brunetti, F. et al. Printed solar cells and energy storage devices on paper temperature stabilization. The substrate and MoO3 precursor were then loaded into substrates. Adv. Funct. Mater. 29, 1806798 (2019). the growth area of the furnace to start the growth. Ar is supplied with a flow of 10 7. Zhang, Y. et al. Flexible electronics based on micro/nanostructured paper. sscm. After 10 min growth at 750 °C, the furnace is left to cool naturally. The Adv. Mater. 30, 1801588 (2018). synthesized MoS2 film is transferred from the native sapphire substrate to the paper 8. Zschieschang, U. & Klauk, H. Organic transistors on paper: a brief review. J. substrates65. Prior to the film transfer, MoS2 is patterned to obtain a stripped Mater. Chem. C. 7, 5522–5533 (2019). NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications 7 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-17297-z 9. Akinwande, D., Petrone, N. & Hone, J. Two-dimensional flexible 42. Gao, Q. et al. Scalable high performance radio frequency electronics based on nanoelectronics. Nat. Commun. 5, 5678 (2014). large domain bilayer MoS2. Nat. Commun. 9, 4778 (2018). 10. Franklin, A. D. Nanomaterials in transistors: from high-performance to thin- 43. Veeralingam, S. & Badhulika, S. 2D - SnSe2 nanoflakes on paper with 1D - film applications. Science 349, aab2750-1–aab2750-9 (2015). NiO gate insulator based MISFET as multifunctional NIR photo switch and 11. Hernandez, Y. et al. High-yield production of graphene by liquid-phase flexible temperature sensor. Mater. Sci. Semicond. Process. 105, 104738 (2020). exfoliation of graphite. Nat. Nanotechnol. 3, 563–568 (2008). 44. Huang, J. et al. Highly transparent and flexible nanopaper transistors. ACS 12. Torrisi, F. et al. Inkjet-printed graphene electronics. ACS Nano 6, 2992–3006 Nano 7, 2106–2113 (2013). (2012). 45. Minari, T. et al. Room-temperature printing of organic thin-film transistors 13. Finn, D. J. et al. Inkjet deposition of liquid-exfoliated graphene and MoS2 with π-junction gold nanoparticles. Adv. Funct. Mater. 24, 4886–4892 (2014). nanosheets for printed device applications. J. Mater. Chem. C. 2, 925–932 (2014). 46. Fujisaki, Y. et al. Transparent nanopaper-based flexible organic thin-film 14. Withers, F. et al. Heterostructures produced from nanosheet-based inks. Nano transistor array. Adv. Funct. Mater. 24, 1657–1663 (2014). Lett. 14, 3987–3992 (2014). 47. Hyun, W. J. et al. All-printed, foldable organic thin-film transistors on glassine 15. Carey, T. et al. Fully inkjet-printed two-dimensional material field-effect paper. Adv. Mater. 27, 7058–7064 (2015). heterojunctions for wearable and textile electronics. Nat. Commun. 8, 1202 48. Dai, S. et al. Intrinsically ionic conductive cellulose nanopapers applied as all solid (2017). dielectrics for low voltage organic transistors. Nat. Commun. 9, 2737 (2018). 16. McManus, D. et al. Water-based and biocompatible 2D crystal inks for all- 49. Kraft, U. et al. Low-voltage, high-frequency organic transistors and unipolar inkjet-printed heterostructures. Nat. Nanotechnol. 12, 343–350 (2017). and complementary ring oscillators on paper. Adv. Electron. Mater. 5, 17. Hu, G. et al. Functional inks and printing of two-dimensional materials. 1800453 (2019). Chem. Soc. Rev. 47, 3265–3300 (2018). 50. Casula, G. et al. Printed, low-voltage, all-organic transistors and complementary 18. Manzeli, S., Ovchinnikov, D., Pasquier, D., Yazyev, O. V. & Kis, A. 2D circuits on paper substrate. Adv. Electron. Mater. 1901027, 1–9 (2020). transition metal dichalcogenides. Nat. Rev. Mater. 2, 17033 (2017). 51. Martins, R. F. P. et al. Recyclable, flexible, low-power oxide electronics. Adv. 19. Gong, Y., Carozo, V., Li, H., Terrones, M. & Jackson, T. N. High flex cycle Funct. Mater. 23, 2153–2161 (2013). testing of CVD monolayer WS2 TFTs on thin flexible polyimide. 2D Mater. 3, 52. Thiemann, S. et al. Cellulose-based ionogels for paper electronics. Adv. Funct. 0–6 (2016). Mater. 24, 625–634 (2014). 20. Kelly, A. G. et al. All-printed thin-film transistors from networks of liquid- 53. Kim, S. J. et al. Nonvolatile memory thin-film transistors using biodegradable exfoliated nanosheets. Science 356, 69–73 (2017). chicken albumen gate insulator and oxide semiconductor channel on eco- 21. Kelly, A. G., Vega-Mayoral, V., Boland, J. B. & Coleman, J. N. Whiskey-phase friendly paper substrate. ACS Appl. Mater. Interfaces 7, 4869–4874 (2015). exfoliation: exfoliation and printing of nanosheets using Irish whiskey. 2D 54. Gaspar, D. et al. Planar dual‐gate paper/oxide field effect transistors as Mater. 6, 045036 (2019). universal logic gates. Adv. Electron. Mater. 4, 1800423 (2018). 22. Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single- 55. Wang, X., Gao, Y., Liu, Z., Luo, J. & Wan, Q. Flexible low-voltage IGZO thin- layer MoS2 transistors. Nat. Nanotechnol. 6, 147–150 (2011). film transistors with polymer electret gate dielectrics on paper substrates. IEEE 23. Li, J., Naiini, M. M., Vaziri, S., Lemme, M. C. & Östling, M. Inkjet printing of Electron Device Lett. 40, 224–227 (2019). MoS2. Adv. Funct. Mater. 24, 6524–6531 (2014). 56. Liu, N., Yun, K. N., Yu, H.-Y., Shim, J. H. & Lee, C. J. High-performance 24. Tong, X., Ashalley, E., Lin, F., Li, H. & Wang, Z. M. Advances in MoS2-based carbon nanotube thin-film transistors on flexible paper substrates. Appl. Phys. field effect transistors (FETs). Nano-Micro Lett. 7, 203–218 (2015). Lett. 106, 103106 (2015). 25. Park, S. & Akinwande, D. First demonstration of high performance 2D 57. Yoon, J. et al. Flammable carbon nanotube transistors on a nitrocellulose monolayer transistors on paper substrates. In 2017 IEEE International paper substrate for transient electronics. Nano Res. 10, 87–96 (2017). Electron Devices Meeting (IEDM) 5.2.1–5.2.4 (IEEE, 2017). 58. Yoon, J. et al. Highly flexible and transparent multilayer MoS2 transistors with 26. Choi, M. et al. Flexible active-matrix organic light-emitting diode display graphene electrodes. Small 9, 3295–3300 (2013). enabled by MoS2 thin-film transistor. Sci. Adv. 4, 1–8 (2018). 59. Lan, Y.-W. et al. Scalable fabrication of a complementary logic inverter based on 27. Lin, Z. et al. Solution-processable 2D semiconductors for high-performance MoS2 fin-shaped field effect transistors. Nanoscale Horiz. 4, 683–688 (2019). large-area electronics. Nature 562, 254–258 (2018). 60. Razavi, B. Design of Analog CMOS Integrated Circuits. 2nd edn, 704 28. Sahatiya, P. & Badhulika, S. Wireless, smart, human motion monitoring using (McGraw-Hill Education, 2005). solution processed fabrication of graphene-Mos2 transistors on paper. Adv. 61. Wang, Z. et al. Current mirror array: a novel circuit topology for combining Electron. Mater. 4, 1700388 (2018). physical unclonable function and machine learning. IEEE Trans. Circuits Syst. 29. Kim, T.-Y. et al. Electrical properties of synthesized large-area MoS2 field- I Regul. Pap. 65, 1314–1326 (2018). effect transistors fabricated with inkjet-printed contacts. ACS Nano 10, 62. Coleman, J. N. et al. Two-dimensional nanosheets produced by liquid 2819–2826 (2016). exfoliation of layered materials. Science 331, 568–571 (2011). 30. Kim, T.-Y. et al. Transparent large-area MoS2 phototransistors with inkjet- 63. Calabrese, G. et al. Inkjet-printed graphene Hall mobility measurements and printed components on flexible platforms. ACS Nano 11, 10273–10280 low-frequency noise characterization. Nanoscale 12, 6708–6716 (2020). (2017). 64. Dumcenco, D. et al. Large-area epitaxial monolayer MoS2. ACS Nano 9, 31. Lim, Y. R. et al. Roll-to-roll production of layer-controlled molybdenum 4611–4620 (2015). disulfide: a platform for 2D semiconductor-based industrial applications. Adv. 65. Gurarslan, A. et al. Surface-energy-assisted perfect transfer of centimeter-scale Mater. 30, 1705270 (2018). monolayer and few-layer MoS2 films onto arbitrary substrates. ACS Nano 8, 32. Xu, X. et al. High‐performance monolayer MoS2 films at the wafer scale by 11522–11528 (2014). two‐step growth. Adv. Funct. Mater. 29, 1901070 (2019). 33. Rice, C. et al. Raman-scattering measurements and first-principles calculations of strain-induced phonon shifts in monolayer MoS2. Phys. Rev. B 87, 081307 Acknowledgements (2013). We acknowledge the ERC PEP2D (contract no. 770047) and H2020 WASP (contract no. 34. Worsley, R. et al. All-2D material inkjet-printed capacitors: toward fully 825213) for financial support. C.Ca., C.Co., G.F.,T.M. acknowledge the Graphene Flag- printed integrated circuits. ACS Nano 13, 54–60 (2019). ship Core 3 (contract no. 881603). R.W. acknowledges the Hewlett-Packard Company 35. Lu, S. et al. Flexible, print-in-place 1D–2D thin-film transistors using aerosol for financial support in the framework of the Graphene NOWNANO Centre for Doc- jet printing. ACS Nano 13, 11263–11272 (2019). toral Training;. C.Ca. acknowledges useful discussions with Alessandro Molle, and 36. Almora, O. et al. Capacitive dark currents, hysteresis, and electrode financial support from the Grand Challenge EPSRC grant EP/N010345/1. S.P. and C.Co polarization in lead halide perovskite solar cells. J. Phys. Chem. Lett. 6, acknowledge financial support from Compagnia di San Paolo (project STRATOS). 1645–1652 (2015). 37. Kong, D. et al. Capacitance characterization of elastomeric dielectrics for applications in intrinsically stretchable thin film transistors. Adv. Funct. Author contributions Mater. 26, 4680–4686 (2016). R.W., S.M. developed the inks under the supervision of C.Ca.; D.K.P., M.P., S.P., D.H.K., 38. Dutta, K., Hazra, A. & Bhattacharyya, P. Ti/TiO2 nanotube array/Ti capacitive and F.F. carried out the MoS2 growth and the transfer on the paper substrates, and device for non-polar aromatic hydrocarbon detection. IEEE Trans. Device performed the Raman spectroscopy and imaging under the supervision of T.M and Mater. Reliab. 16, 235–242 (2016). C.Co.; S.C., L.P., G.C., and G.F. fabricated the electronic devices, performed the electrical 39. International Technology Roadmap for Semiconductors–ITRS. Available at: measurements, and analyzed the results; G.F, G.I., and M.M. designed and supervised the http://www.itrs2.net/. research. All authors discussed the results and contributed to the manuscript. 40. Zheng, J. et al. High-mobility multilayered MoS2 flakes with low contact resistance grown by chemical vapor deposition. Adv. Mater. 29, 1604540 (2017). 41. Wachter, S., Polyushkin, D. K., Bethge, O. & Mueller, T. A microprocessor Competing interests based on a two-dimensional semiconductor. Nat. Commun. 8, 14948 (2017). The authors declare no competing interests. 8 NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-17297-z ARTICLE Additional information Open Access This article is licensed under a Creative Commons Supplementary information is available for this paper at https://doi.org/10.1038/s41467- Attribution 4.0 International License, which permits use, sharing, 020-17297-z. adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Correspondence and requests for materials should be addressed to G.F. Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless Peer review information Nature Communications thanks the anonymous reviewers for indicated otherwise in a credit line to the material. If material is not included in the their contribution to the peer review of this work. Peer review reports are available. article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from Reprints and permission information is available at http://www.nature.com/reprints the copyright holder. To view a copy of this license, visit http://creativecommons.org/ licenses/by/4.0/. Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. © The Author(s) 2020 NATURE COMMUNICATIONS | (2020)11:3566 | https://doi.org/10.1038/s41467-020-17297-z | www.nature.com/naturecommunications 9