(PDF) Structural adders reduction in fixed coefficient transposed direct form FIR filters

International Journal of Engineering and Technical Research (IJETR) ISSN: 2321-0869, Volume-3, Issue-2, February 2015 Structural adders reduction in fixed coefficient transposed direct form FIR filters Raval Jay Manoj, S. Umadevi  Abstract— Over the last two decades, fixed coefficient FIR filters were generally optimized by minimizing the number of adders required to implement the multiplier block in the transposed direct form filter structure. In this paper, an optimization method for the structural adders in the transposed tapped delay line is proposed. Although additional registers are required, an optimal trade-off can be made such that the overall combinational logic is reduced. For a majority of taps, the delay through the structural adder is shortened except for the last tap. The one full adder delay increase for the last optimized tap is tolerable as it does not fall in the critical path in most cases. The criterion for which area reduction up to 4.5% to 9.5% and power reduction up to 10% to 30% for the structural adder block of three benchmarks filters is estimated theoretically. The saving is more prominent as the number of taps grows. The criterion for which reduction in number LUTs, number of Fig. 1 Transposed direct form FIR Filter. bonded IOBs, & number of slices are derived. Actual synthesis For fixed coefficient FIR filters, the bit widths of the input results are obtained by Xilinx design ISE suite 14.3 (Sparten 3E and all coefficients are known. This enables the bit width of family and device-XC3S100) & Cadence RTL compiler with the coefficient multiplier to be determined from its dynamic 0.18μm TSMC CMOS libraries. range. As the partial sums are delayed before they are added with the coefficient multiplier outputs in the structural adders, Index Terms— FIR filter, Normal structural adder, the bit widths of the structural adders increase monotonically proposed structural adder reduction, Xilinx design ISE suite from the first structural adder towards the output. Careful 14.3 (Sparten 3E family and device-XC3S100) and Cadence analysis revealed that for most filters, the bit width of the RTL compiler with, 0.18μm TSMC CMOS libraries, Area & adder increases only from coefficient N−1 to about N/2, after Power reduction. which the bit width stays relatively constant and increases by no more than two bits. As the bit width of the coefficient I. INTRODUCTION multiplier output reduces towards the last tap, longer sign The inherit stability makes FIR filters a preferred choice in extension is required for these structural adders. This paper digital signal processing. As wireless technology advances, proposes an addition scheme to reduce the bit widths of these FIR filters with shorter transition bands, more stringent structural adders so that the total combinational logic is stopband attenuation requirement and higher sampling rate, reduced at the expense of some register overhead. To are in great demand. To achieve these goals, ASIC determine if the area reduction is able to offset the overheads implementation is necessary. The Transposed Direct Form of additional adders and registers, a lower bound for the (TDF) structure is preferred over direct form structure for difference between the adder bit width and the coefficient higher order ASIC filters due to its shorter critical path delay. multiplier output bit width is established analytically. In the direct form structure, the input is delayed before the coefficient multiplication and the register length of each tap is fixed by the input bit width. In the TDF structure, the partial II. PROPOSED STRUCTURAL ADDER OPTIMIZATION sums generated by the outputs of the coefficient multiplier, are delayed. Thus, the lengths of the registers increase The fundamental concept of our proposed method can be monotonically along the taps to hold the correct precision of illustrated by an example in decimal. Let {610,−274, 2, 258} the partial sums. Consequently, the number of registers be a set of coefficient multiplier outputs to be accumulated to needed for the TDF structure is larger than that for the direct a large partial sum 1234567 by the structural adders in a form. tapped delay line. A downright approach is to add one number Fig. 1 shows a generic TDF fixed coefficient FIR filter. For at a time from the set of smaller integers to the large integer. long filters, the shorter critical path of the TDF is more Alternatively, the integers in the set are summed and then significant than the costs of the registers. added to the large integer. The latter accumulation scheme, when implemented in hardware, requires the large integer and the smaller integers to be stored at each tap. This incurs a Manuscript received February 06, 2015. large register overhead, which can be reduced if the large Raval Jay Manoj, M.Tech, SENSE Department, VIT University, Tamilnadu, India. number is split into two smaller integers as shown in Fig. 2. S. Umadevi, SENSE Department, VIT University, Tamilnadu, India. 61 www.erpublication.org Structural adders reduction in fixed coefficient transposed direct form FIR filters Normal adders method: Proposed adders method: Fig. 4 Proposed & Normal adder method Fig. 2 Example of adders size reductions for decimal number A. RTL Schematic of adders accumulation. By partitioning the large integer into two halves, the register overhead is greatly reduced as only the fourth overlapping digit has to be saved twice. The additional adder at the last step needs only a four-digit addition as the three least significant digits are all zeros. Besides, the reduction of the dynamic ranges of the operands also simplifies the structural adder implementation and reduced the length of sign extension. Fig. 5 RTL Schematic of proposed & normal adders The fig. 5 is shows the RTL schematic of proposed & Normal adders. The simulation output for the above adder method is shown in below: B. Simulation output of adder Fig. 3 Binary example on the optimization of last three adders of Fig. 2. Fig. 6 Simulation output of normal & proposed adder Fig.3 shows the binary implementation of the proposed scheme on the last three coefficients of the filter example from C. Simulation report of normal & proposed adder: Fig. 2. The reduction of adder lengths is observed to be several times more than the register and adder overheads it The Simulation Report of the above methods is given by incurred. Furthermore, the delays through the structural Xilinx design ISE suite 14.3 with Spartan 3E family is shown adders, a2 and a1 have been reduced, while the delay through in Table 1. a0 is increased by one Full adder delay. The slight increase in TABLE 1 the delay through a0 is not an issue as in most cases, there Number LUTs, Number of bonded IOBs, & Number of slices exists at least one tap (i >0) for which delay(x·c0) < Calculation delay(x·ci). The full adder reduction for the structural adders can be offset by the increase in flip-flop overhead. Therefore, Logic Used Available Utilization information about the minimal difference between the utilization addends of the structural adders is of interest. Propose Normal Proposed Normal d Number 54 33 2448 2% 1% of slices III. NORMAL & PROPOSED ADDERS Number IMPLEMENTATION: of LUTs 103 60 4896 2% 1% Number Take partial sum is large like 1234567 & coefficients are of bonded 104 96 108 96% 88% {610, 214, 306, 3} of the TDF FIR filters. Now solution is IOBs given by the below method Fig. 4. 62 www.erpublication.org International Journal of Engineering and Technical Research (IJETR) ISSN: 2321-0869, Volume-3, Issue-2, February 2015 IV. TRANSPOSED DIRECT FORM FIR FILTER (TDF) The Simulation Report of the above methods is given by BY USING NORMAL & PROPOSED ADDER METHOD: Xilinx design ISE suite 14.3 with Spartan 3E family is shown in Table 2. A. RTL Schematic of TDF FIR filter TABLE 2 Number LUTs, Number of bonded IOBs, & Number of slices The TDF FIR filter RTL Schematic is shown in below fig. 7. Calculation of TDF FIR filter Logic utilizatio Used Available Utilization n Normal Proposed Normal Proposed Number 247 81 2448 16% 4% of slices Number 124 40 4896 6% 2% of LUTs Number of bonded 100 36 108 151% 54% IOBs TABLE 3 Area & Power Calculation of TDF FIR Filter Fig. 7 RTL Schematic of TDF FIR filter Area analysis(micro-meter) Power Analysis(nWatts) B. Simulation output of TDF FIR filter Normal Proposed Normal Proposed 11249 5430 405235.5 99615.7 1. Simulation output of TDF FIR filter by using normal adder method: V. IMPLEMENTATION RESULTS The fig. 6 is shows the simulation output of normal and proposed adder and this results is verified by Xilinx design ISE suite 14.3 (Sparten 3E family & device-XC3S100). In Table 1 comparison between normal & proposed adder is shown. The fig. 8 and fig. 9 is shows the simulation output of TDF FIR Filters by normal method and proposed method. This result is verified by Xilinx design ISE suite 14.3 with Spartan 3E family and area and power analysis is verified by Cadence RTL compiler with 0.18μm TSMC CMOS libraries. VI. CONCLUSION This paper presents a new method to reduce the total area and Fig. 8 Simulation output of TDF FIR filter by using normal power of fixed coefficient transposed direct form FIR with a adder method large number of taps by minimizing the bit widths of the structural adders. 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