(PDF) Three-Phase Six-Level Multilevel Voltage Source Inverter: Modeling and Experimental Validation

Article Three-Phase Six-Level Multilevel Voltage Source Inverter: Modeling and Experimental Validation Sheikh Tanzim Meraj 1, Nor Zaihar Yahaya 1, Kamrul Hasan 2, Molla Shahadat Hossain Lipu 3,4,*, Ammar Masaoud 5, Sawal Hamid Md Ali 3, Aini Hussain 3, Muhammad Murtadha Othman 2 and Farhan Mumtaz 1 1 Department of Electrical and Electronic Engineering, Universiti Teknologi PETRONAS, Perak 32600, Malaysia;

(S.T.M.);

(N.Z.Y.);

(F.M.) 2 Solar Research Institute (SRI), Universiti Teknologi MARA, Shah Alam 40450, Malaysia;

(K.H.);

(M.M.O.) 3 Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi 43600, Malaysia;

(S.H.M.A.);

(A.H.) 4 Centre for Automotive Research (CAR), Universiti Kebangsaan Malaysia, Bangi 43600, Malaysia 5 Faculty of Mechanical and Electrical Engineering, Al Baath University, Homs 22743, Syria;

* Correspondence:

Abstract: This research proposes a three-phase six-level multilevel inverter depending on twelve- switch three-phase Bridge and multilevel DC-link. The proposed architecture increases the number of voltage levels with less power components than conventional inverters such as the flying capac- Citation: Meraj, S.T.; Yahaya, N.Z.; itor, cascaded H-bridge, diode-clamped and other recently established multilevel inverter topolo- Hasan, K.; Hossain Lipu, M.S.; gies. The multilevel DC-link circuit is constructed by connecting three distinct DC voltage supplies, Masaoud, A.; Ali, S.H.M.; Hussain, such as single DC supply, half-bridge and full-bridge cells. The purpose of both full-bridge and half- A.; Othman, M.M.; Mumtaz, F. bridge cells is to provide a variable DC voltage with a common voltage step to the three-phase Three-Phase Six-Level Multilevel bridge’s mid-point. A vector modulation technique is also employed to achieve the desired output Voltage Source Inverter: Modeling voltage waveforms. The proposed inverter can operate as a six-level or two-level inverter, depend- and Experimental Validation. ing on the magnitude of the modulation indexes. To guarantee the feasibility of the proposed con- Micromachines 2021, 12, 1133. figuration, the proposed inverter’s prototype is developed, and the experimental results are pro- https://doi.org/10.3390/mi12091133 vided. The proposed inverter showed good performance with high efficiency of 97.59% following the IEEE 1547 standard. The current harmonics of the proposed inverter was also minimized to only Academic Editor: Francisco J. 5.8%. Perez-Pinal Keywords: multilevel inverter; power electronics; staircase modulation; vector modulation Received: 4 September 2021 Accepted: 16 September 2021 Published: 21 September 2021 Publisher’s Note: MDPI stays neu- 1. Introduction tral with regard to jurisdictional In the sector of power engineering, multilevel inverters (MLIs) have been developed claims in published maps and institu- and their applications have been expanded in a rapid manner in recent years. The com- tional affiliations. position of MLIs basically includes a power components’ array and DC voltage sup- plies/capacitors that produce a variable and controllable stepped voltage waveform. Over the years, various MLIs topologies have been proposed and used due to their importance and roles in power conversion systems, with some of the most well-known and conven- Copyright: © 2021 by the authors. Li- tional topologies including the flying capacitor (FC), the cascaded H-bridge (CHB) and censee MDPI, Basel, Switzerland. the neutral point clamped (NPC) inverter. Compared to the conventional two-level in- This article is an open access article distributed under the terms and con- verter, the CHB, FC and NPC multilevel inverters exhibit several advantageous features ditions of the Creative Commons At- such as low voltage stress, low total harmonic distortions (THD), low switching losses, tribution (CC BY) license (http://crea- high electro-magnetic compatibility and high-quality output voltage with high efficiency tivecommons.org/licenses/by/4.0/). [1–4]. Micromachines 2021, 12, 1133. https://doi.org/10.3390/mi12091133 www.mdpi.com/journal/micromachines Micromachines 2021, 12, 1133 2 of 16 To date, MLIs have been extensively used to control variable frequency drivers [5], static VAR compensators [6,7], HVDC systems [8], un-interrupted power supplies (UPS) and PV grid connected systems and renewable energy resources. By increasing the reso- lution of stepped voltage, the power quality of MLIs can be significantly improved. How- ever, this process can significantly increase the number of power electric components count, installation area along with increased cost and control complications. Thus, the in- creased cost of the system and complexity of the inverter generally can limit the amount of voltage levels produced by any MLI structure. To mitigate and balance out this particular issue, many variations of MLI topologies have been proposed in recent years to enhance their capability and utilize them in various industrial applications. Advanced NPC (ANPC) [9], the stacked MC [10], symmetrical and asymmetrical CHB are some notable examples [11–14]. Symmetrical MLIs utilize DC volt- age sources of equal magnitudes and can have certain beneficial features such as, stand- ardized control, lower voltage stresses on semiconductor devices, modular structure, etc. Hybrid MLIs are some alternative inverters that are built using the combination of two or more MLI topologies. These inverters are generally designed using DC supplies of une- qual magnitudes. These MLIs can generate higher voltage levels utilizing less amount of power equipment and using a high voltage ratio of DC supplies [15,16]. Although asym- metry and hybridization can increase the number of voltage levels, these MLI topologies usually generate a high total standing voltage (TSV) on power electric components which in turn can increase the overall system cost, increase the voltage ratings of switches, de- crease the switching redundancies and also limit the industrial applications. However, in [17], a novel family of MLI structures was designed using half-bridge inverter and multi- level DC-link. These variations in inverter topologies may produce even higher voltage levels utilizing abridged amount of power components. The goal of the multilevel DC-link is to provide the H-bridge with successive positive voltage levels starting from zero voltage, whereas the purpose of the half-bridge is to pro- vide the desired outputs comprising of negative and positive voltage. The aforementioned method has been utilized to propose different three-phase cascaded MLI topologies which are presented in [18–20]. To further decrease the overall amount of DC supplies and switches in these topologies, a new multilevel inverter configuration has been recently suggested in [21–24]. These MLIs were built by utilizing the combination of a twelve- switch three-phase Bridge and a multilevel DC-link. The multilevel DC-link is constructed by a fixed supply of cascaded H-bridge power modules and DC voltage. Comparing with the available MLI topologies, the projected configuration comes with more voltage levels and lesser power components. In this study, an improved MLI is configured that can synthesize six-level output by using the combination of a conventional twelve-switch three-phase bridge and a modified multilevel DC-link. The multilevel DC-link is composed of only one DC voltage supply, H-bridge and full-bridge power cells. Both of the H-bridge and full-bridge modules are controlled, and the proposed inverter generates a stair-case waveform of eleven symmet- rical line-to-line voltage levels. The proposed inverter needs to be operated under a certain condition where the modulation index is more than 0.98 to generate 11 voltage levels. On the other hand, the inverter can generate a stair-case waveform of nine asymmetrical lines to line voltage levels if the modulation index is equal to 0.98. Furthermore, if the modula- tion index decreases below 0.98, the MLI operates identically to a traditional two-level three-phase inverter and accordingly three symmetrical voltage levels are seen in its line- to-line output voltage waveforms. This research offers the following key contributions:  The advantages of both multilevel DC-links and H-bridge circuits have been inher- ited by the suggested topology. The proposed MLI has been able to lower total volt- age stress and generate greater voltage levels with fewer components because of this smart design. Micromachines 2021, 12, 1133 3 of 16  Since it does not contain switched capacitors, the proposed MLI does not require a complex control approach or additional circuits to deal with voltage balancing or ex- cessive power losses.  Depending on the application needs, the proposed topology can be modified to achieve higher voltage levels.  The suggested MLI’s modularity and smart switching arrangements have allowed it to perform in four different ways depending on the modulation indices. This has provided the MLI with more flexibility and reliability. The paper is organized into 6 sections. The MLI topology and its operation are stud- ied in Section 2. Section 2 further discusses the efficiency, extended version of the MLI and the implementation of vector modulation technique. Section 3 shows the detailed simula- tion results of the proposed MLI. The comparison of this MLI with classical and recent MLI topologies is discussed in Section 4. Section 5 contains the experimental results, and Section 6 concludes the paper. 2. Operating Principle of Three-Phase MLI 2.1. Proposed Topology The circuit diagram of the proposed three-phase six-level MLI topology is depicted in Figure 1. Six unidirectional switches formed by (S1~S6) and (Da1~Dc2) diodes are con- nected with a classical three-phase six-switch (Q1~Q6) to build the main bridge. On the other hand, a single DC voltage supply, a half-bridge cell consisting of two switches (Ta1, Ta2) and a single DC supply along with a full-bridge power cell comprising four switches (Tb1~Tb4) and a DC supply are connected together to form a multilevel DC-link voltage. The DC voltages for half-bridge and full-bridge power cells are 3Vdc and Vdc, respec- tively, while the DC voltage for a single supply is 2Vdc. The power cell switches are turned on/off to synthesize four consecutive voltage levels: 4Vdc, 3Vdc, 2Vdc and Vdc at the middle point (o) relating to the inverter’s ground. Table 1 illustrates the switching operation of the proposed inverter. Figure 1. Proposed structure of a three-phase six-level inverter. Micromachines 2021, 12, 1133 4 of 16 Table 1. Switching states for the proposed six-level inverter (Ma ≥ 0.98). Sa Q1 S1 S2 Q2 Ta1 Ta2 Tb1 Tb2 Tb3 Tb4 Vag 5 1 0 0 0 0 0 0 0 0 0 +5Vdc 4 0 1 1 0 1 0 0 1 1 0 +4Vdc 3 0 1 1 0 1 0 0 1 0 1 +3Vdc 2 0 1 1 0 1 0 1 0 0 1 +2Vdc 1 0 1 1 0 0 1 0 1 1 0 +Vdc 0 0 0 0 1 0 0 0 0 0 0 0 It is worth mentioning that the switching states demonstrated in Table 1 are applica- ble for all three phases. For phase b and c, it should be Q3, Q4, S3, S4 and Q5, Q6, S5, S6, respectively instead of Q1, Q2, S1, S2. The switching configuration of the proposed MLI is given in the following equation: 𝑉𝑎𝑔 𝑆𝑎 5𝑉𝑑𝑐 𝑉𝑏𝑔 = × 𝑆𝑏 (1) 𝑉𝑐𝑔 𝑁−1 𝑆𝑐 where Sa, Sb and Sc are switching positions. Vag, Vbg and Vcg are the MLI’s line to ground voltages and N = 6 is the number of voltage levels. Since the topology employed for the proposed MLI is modeled to obtain the three-phase well-adjusted line to line output volt- ages producing the highest number of voltage levels, a suitable switching structure is needed for generating the MLI’s gate pulses. Consecutively, these switching states gener- ate the gate pulses and drive the studied MLI under all modulation indexes. Different modulation techniques have been suggested to control the multilevel inverters. These modulation methods are categorized depending on the operating switching frequency [25]. The low frequency modulation method known as selective harmonic elimination (SHE-PWM) is usually employed to predefine and pre-calculate the optimal switching angles. To obtain a solution for the angles, a set of equations is normally solved offline using numerical methods [26,27]. The proposed MLI can be easily controlled, and the de- sired outputs can be simply achieved with regard to the MLI’s switching states Sa, Sb and Sc. Therefore, a new modulation method was recently suggested in [28] where each phase in the proposed inverter is controlled independently. For a given modulation index Ma, the inverter’s switching states Sa, Sb and Sc are determined with respect to the MLI’s line to ground reference voltages Vag_ref, Vbg_ref and Vcg_ref. The correlation among the MLI’s reference line to ground voltages and the respective switching sequences is: 𝑆𝑎 𝑉𝑎𝑔_𝑟𝑒𝑓 𝑁−1 𝑆𝑏 = × 𝑉𝑏𝑔_𝑟𝑒𝑓 (2) 5𝑉𝑑𝑐 𝑆𝑐 𝑉𝑐𝑔_𝑟𝑒𝑓 𝑐𝑜𝑠( 𝜔𝑡) 𝑉𝑎𝑔_𝑟𝑒𝑓 1 × 𝑉𝑏𝑔_𝑟𝑒𝑓 = × 𝑐𝑜𝑠( 𝜔𝑡 − ) + × 1− 𝑐𝑜𝑠( 3𝜔𝑡) × 1 . (3) 𝑉𝑐𝑔_𝑟𝑒𝑓 𝑐𝑜𝑠( 𝜔𝑡 + ) 1 According to (3), the 3rd harmonic element is added to MLI’s line to ground reference voltage waveforms. Therefore, Ma can extend to 1.15 without instigating over modulation. 2.2. Extended Structure The multistep DC-link circuit can be extended by keeping the proposed MLI’s main bridge construction. This enables the proposed inverter to achieve a higher amount of voltage steps using a small quantity of power equipment. To extend the multistep DC- link circuit, the half-bridge power module and (n) multiple units of full-bridge power modules are connected following series connection to generate (N – 1) sequent voltage steps as depicted in Figure 2. For full-bridge power cells: Micromachines 2021, 12, 1133 5 of 16 𝑉𝑑𝑐_𝑓𝑏1 = 3( ) 𝑉𝑑𝑐 (4) 𝑉𝑑𝑐_𝑓𝑏𝑛 = 3( ) 𝑉𝑑𝑐. (5) For half-bridge power cells: 𝑉𝑑𝑐_ℎ𝑏 = 3( ) 𝑉𝑑𝑐. (6) For a single DC voltage supply: ( ) 𝑉𝑑𝑐_𝑠 = 𝑉𝑑𝑐 + ∑ 3( ) 𝑉𝑑𝑐 = 𝑉𝑑𝑐. (7) Hence, the highest number of voltage steps that can be achieved are: 𝑁 = (1 + 3( ) ). (8) Here, N = [6, 15, 42, 123, ........]. The total required numbers of IGBTs (M_sw) and DC supplies (M_DC) in terms of voltage steps are given as: 2 𝑀_𝑠𝑤 = 4𝐿𝑜𝑔 ( 𝑁 − 1) + 14 (9) 3 𝑀_𝐷𝐶 = 𝐿𝑜𝑔 ( 𝑁 − 1) + 2. (10) Figure 2. Proposed structure of three-phase N-level multilevel inverter. 2.3. Efficiency Calculation It is important to validate the two principal losses that generally occur during the operation of switching devices. These losses are classified as conduction losses and switching losses. Conduction losses (PConduction) are defined as the losses of power electronic devices during on-state. In this case, both the diode and the switches are taken into con- sideration. The instantaneous conduction losses of the IGBT and diodes can be determined using (11) and (12), respectively. PConduction_IGBT (t) = [VIGBT + RIGBT i(t)] × i(t) (11) PConduction_Diode (t) = [VDiode + RDiode i(t)] × i(t) (12) Micromachines 2021, 12, 1133 6 of 16 Here, VIGBT is the voltage of IGBTs while VDiode is the voltage of the diodes when these devices are activated. Again, RIGBT is the corresponding resistance of IGBTs while RDiode represents the corresponding resistance of the diodes. The subsequent results are then summed to calculate the conduction losses of the proposed MLI. Switching losses (PSwitching) are defined as the losses of power electronic modules when they are activated and deactivated. Switching loss is proportional to the switching fre- quency. The activation (Won) and deactivation (Woff) energy loss of these modules are ob- tained by: ton vswitch I Won = t − (t − ton dt. (13) ton ton 0 toff vswitch I Woff = t − (t − toff dt. (14) toff toff 0 Here, ton and toff are the turn-on time and turn-off time of the IGBTs consecutively. I represents the current through the IGBT devices before/after they are turned off/on. vswitch demonstrates the forward voltage drop for the IGBTs. Thus, Nswitch Non Noff Pswitch = f Won,i + Woff,i (15) i=1 i=1 i=1 where f, Non and Noff are the fundamental frequency and the number of times each switch is turned on and off during a time period of t, respectively. Again, Won,i and Woff,i are the energy loss of each switch turning on and off for ith time. Thus, the total loss (PTotal) can be calculated as follows: PTotal = Pconduction + Pswitching. (16) The following parameters are considered for calculating the power loss of the pro- posed module: VIGBT = 2.4 V, RIGBT = 0.052 Ω, VDiode = 2 V and RDiode = 0.1 Ω, f = 50 Hz, ton = toff = 1. The proposed inverter is running under the conditions: Total DC-link voltage = 450 V, Ma = 1, f = 50 Hz, and Pout = 3.6 kW. Again, a single-phase resistive inductive load (237 Ω˗0.53 H) is connected with the module as the output. The calculation is conducted for each switch and diode for one period and applying (11) to (16) the total losses (PTotal) of the inverter is evaluated to be 88.75 W operating for 1 s. Therefore, the proposed inverter efficiency is 97.59%. This has passed the IEEE 1547 standard for interconnected devices of power grids. 2.4. Switching Pulses Generation Using Nearest Vector Modulation The goal of the modulation strategy is to produce the appropriate switching pulses by determining the MLI’s switching states. The operating block diagram of the nearest vector modulation (NVM) technique is shown in Figure 3. The space vector illustration of the operation of the projected MLI in stationary α−β location frame is obtained as follows: 5𝑉𝑑𝑐 𝑉𝛼 = × (2𝑆𝑎 − 𝑆𝑏 − 𝑆𝑐) (17) 3(𝑁 − 1) 5𝑉𝑑𝑐 𝑉𝛽 = × (𝑆𝑐 − 𝑆𝑏) (18) √3(𝑁 − 1) 𝑉 = 𝑉𝛼 − 𝑗𝑉β. (19) Micromachines 2021, 12, 1133 7 of 16 Figure 3. Operating principle of the NVM technique. Four different space vector diagrams representing the function of the three-phase MLI with four valid switching sequences are shown in Figure 4. -Vβ 550 -Vβ 450 540 450 540 350 530 350 440 530 250 520 250 520 150 510 Vα 150 510 Vα 050 500 151 511 051 501 501 051 052 502 052 502 053 503 053 503 054 504 054 504 055 505 044 404 045 405 405 035 305 045 025 205 035 305 015 105 025 115 205 005 015 105 (a) (b) -Vβ -Vβ 110 350 440 530 250 520 Vα Vα 010 100 151 511 052 502 053 503 011 101 044 404 035 305 025 115 205 001 (c) (d) Figure 4. Space vector diagrams for the proposed MLI at: (a) Ma = 1.3, (b) Ma = 1.15, (c) Ma = 0.98 and (d) Ma = 0.8. 3. Simulation Results According to these space vector diagrams shown in Figure 4, the switching states of the proposed MLI can be classified into four categories. (1) In case of Ma ≥ 1.2, the resultant switching state compromises of 30 various group- ings of switching sequences (active vectors) are as follows: {055-054-053-052-051-050-150- 250-350-450-550-540-530-520-510-500-501-502-503-504-505-405-305-205-105-005-015-025- 035-045}. For instance: at Ma = 1.3, Figure 5a shows the instantaneous values of Sa, Sb and Sc and switching pulses arrangements within a full cycle of operation. These switching states allow the proposed MLI to produce a three-phase stable staircase 11 level line to a line voltage with mutual variance of Vdc, which is as follows: 5Vdc, +4Vdc, +3Vdc, +2Vdc, +Vdc, 0, −Vdc, −2Vdc, −3Vdc, −4Vdc, −5Vdc) where Vab, Vbc and Vca are related to Sa, Sb and Sc by: Micromachines 2021, 12, 1133 8 of 16 𝑉𝑎𝑏 1 −1 0 𝑆𝑎 𝑉𝑏𝑐 = × 0 1 −1 × 𝑆𝑏 . (20) 𝑉𝑐𝑎 −1 0 1 𝑆𝑐 The simulated outputs including the MLI’s line to line (Vab), line to neutral (VaN), line to ground (Vag), line to center (Vao) and center to ground (Vog) voltage outputs are illustrated in Figure 5b. 5 Sb 5 5 +5Vdc 4 3 4 3 Sa 4 3 Sc 2 1 0 2 1 0 2 1 0 Vab 0 0 0 0 5 Sa 5 5 0 0 5 5 5 Sb 0 5 0 0 Sc 0 0 +10Vdc/3 5 0 Tb1 5 5 5 0 VaN Tb4 Tb2 Tb3 +4Vdc Ta2 Vao Ta1 0 Q6 S5&S6 Q5 +4Vdc Vog Q4 S3&S4 Q3 0 Q2 +5Vdc Vag S1&S2 Q1 0 0.01 0.02 0 0.02 0.02 0.03 0.04 Time (s) Time (s) (a) (b) 4 Sb 5 4 Sa 5 4 Sc 5 +5Vdc 3 3 3 2 1 2 1 2 1 Vab 0 0 0 0 4 0 1 Sa 5 4 1 0 5 4 Sb 1 0 1 4 1 0 Sc 1 Tb1 4 5 4 +3Vdc Tb2 0 VaN Tb4 Tb3 +4Vdc Ta2 Vao Ta1 0 Q6 S5&S6 Q5 +4Vdc Vog Q4 S3&S4 Q3 0 +5Vdc Q2 Vag S1&S2 Q1 0 0.01 0.02 0 0.01 0.02 0.03 0.04 Time (s) Time (s) (c) (d) 4 Sb 5 4 Sa 5 4 Sc 5 +5Vdc 3 3 3 2 1 2 1 2 1 Vab 0 0 0 0 1 4 Sa 5 4 1 0 0 4 5 4 Sb 1 0 1 4 4 1 0 Sc 1 Tb1 4 5 4 +8Vdc/3 VaN Tb4 Tb2 0 Tb3 +3Vdc Ta2 Vao Ta1 0 Q6 S5&S6 Q5 +4Vdc Vog Q4 S3&S4 Q3 0 Q2 +5Vdc Vag S1&S2 Q1 0 0.01 0.02 0 0.01 0.02 0.03 0.04 Time (s) Time (s) (e) (f) +5Vdc Vab 1 Sb 1 Sa 1 Sc 0 0 0 0 1 0 1 1 0 0 0 0 Sa 1 1 1 Sb 0 0 0 1 1 0 0 Sc 0 1 1 1 Tb1 Tb2 Tb4 Tb3 Ta2 +10Vdc/3 VaN Ta1 Q6 0 S5&S6 Q5 Q4 S3&S4 Q3 Q2 +5Vdc Vag S1&S2 Q1 0 0.01 0.02 0 0.01 0.02 0.03 0.04 Time (s) Time (s) (g) (h) Figure 5. Simulation results: (a) switching states at Ma = 1.3, (b) simulated waveforms at Ma = 1.3 (c) switching states at Ma = 1.15, (d) simulated waveforms at Ma = 1.15, (e) switching states at Ma = 0.98, (f) simulated waveforms at Ma = 0.98, (g) switching states at Ma = 0.8 and (h) simulated waveforms Ma = 0.8. Micromachines 2021, 12, 1133 9 of 16 (2) For 1.2 > Ma > 0.98, the maneuver of the proposed MLI is organized inside 30 other combinations of switching sequences (active vectors) as follows: {044 (155)-054-053-052- 051-151 (040)-150-250-350-450-440-(551)-540-530-520-510-511 (400)-501-502-503-504-404 (515)-405-305-205-105-115 (004)-015-025-035-045}. The switching sequences of the proposed MLI and its equivalent switching pulses at (for instance: Ma = 1.15) are shown in Figure 5c. Reducing the modulation index affects the peak value voltage. Thus, the amount of line to neutral (VaN) voltage levels of the MLI, in this case, is decreased to 14 voltage levels, as shown in Figure 5d. These voltage levels are as follows: (+9Vdc/3, +8Vdc/3, +7Vdc/3, +6Vdc/3, +4Vdc/3, +3Vdc/3, +Vdc/3, −Vdc/3, −3Vdc/3, −4Vdc/3, −6Vdc/3, −7Vdc/3, −8Vdc/3 and −9Vdc/3). Although this switching cate- gory has decreased the peak voltage and the line to neutral voltage, the number of line to line voltage (Vab) outputs is maintained at 5Vdc with 11 voltage levels (+5Vdc, +4Vdc, +3Vdc, +2Vdc, +Vdc, 0, −Vdc, −2Vdc, −3Vdc, −4Vdc, −5Vdc). From Figure 5d, it can be further observed that utilizing the synthesized switching states, six voltage steps can be generated using multiple combinations of switching se- quences. For example, the voltage levels Vab = −4Vdc, Vbc = 0 and Vca = +4Vdc can be pro- duced applying two valid redundant switching states 044 or (155). Since the switching sequence design should minimize the number of switching instances, the redundant switching states: {(155)-(040)-(551)-(400)-(515)-(004)} are not utilized. (3) For Ma = 0.98, 18 different combinations of switching states (active vectors) are generated to form the new valid switching sequence which is as follows: {044 (155)-053- 052-151 (040)-250-350-440 (551)-530-520-511 (400)-502-503-404 (515)-305-205-115 (004)-025- 035}. Figure 5e depicts the switching sequences of the projected MLI and switching pulses under the condition of Ma = 0.98. It can be observed that the MLI’s line to line voltage (Vab) waveforms reach their highest values of +5Vdc compromising nine voltage levels (+5Vdc, +4Vdc, +3Vdc, +2Vdc, 0, −2Vdc, −3Vdc, −4Vdc, −5Vdc), while the inverter line to neutral volt- ages (VaN) reach their maximum value of +8Vdc/3 with eight voltage steps (+8Vdc/3, +7Vdc/3, +4Vdc/3, +Vdc/3, −Vdc/3, −4Vdc/3, +7Vdc/3, −8Vdc/3). It is worth mentioning that the operation under the condition of Ma = 0.98 makes the common voltage deference in staircase waveform of nine line to line voltage levels fluctuate between Vdc and 2Vdc. As a result, the MLI functions like a three-phase five-level asymmetrical MLI. The simulated staircase waveforms of voltages at Ma = 0.98 are shown in Figure 5f. Similar to the previous case, the six redundant switching states in this switching sequence: {(155)-(040)-(551)-(400)-(515)-(004)} are also not utilized. (4) For Ma < 0.98, the MLI functions like a traditional three-phase two-level MLI. The novel switching sequences are demonstrated in Table 2 (For instance: at Ma = 0.8). The switching sequences tabulated in Table 2 are also applicable for other phases. Table 2. Switching states for the proposed six-level inverter (Ma < 0.98). Sa Q1 S1 S2 Q2 Ta1 Ta2 Tb1 Tb2 Tb3 Tb4 Vag 1 1 0 0 0 0 0 0 0 0 0 +5Vdc 0 0 0 0 1 0 0 0 0 0 0 0 In this case, the MLI’s switching pulses are generated utilizing the switching se- quence shown in Figure 5g. It is identified that the final switching state comprises of six groupings of active vectors: {011-010-110-100-101-001}. Following this switching state leads the projected MLI to obtain the desired output voltage of Vab, VaN and Vag as de- picted in Figure 5h. The extended configuration is also verified by simulating a model for (n = 2). The simulation is done utilizing 10 V voltage supply and a three-phase resistive-inductive load of 237 Ω–0.53 H as output. The nearest vector modulation technique is implemented with a nominal frequency of 50 Hz. The simulation results of fifteen-level line to line output Micromachines 2021, 12, 1133 10 of 16 voltage (Vab) built on the extended model and its equivalent switching pulses are illus- trated in Figure 6a. In addition, the output voltages of VaN, Vao, Vog and Vag are also shown in Figure 6b. 140 Vbc Vab Vca 0 VaN -140 T14 T13 T12 Vao T11 T24 0 T23 T22 T21 Ta2 Ta1 Vog Q6 S5&S6 Q5 Q4 0 S3&S4 Q3 Vag Q2 S1&S2 Q1 0 0.01 0.02 0 0.01 0.02 0.03 0.04 Time (s) Time (s) (a) (b) Figure 6. For (n = 2, N = 15, f = 50 Hz) (a) Switching gate signals and Vab, Vbc and Vca, (b) Simulated waveforms of VaN, Vao, Vog and Vag. 4. Comparative Analysis The major advantage of the proposed MLI configuration is the ability to generate a high amount of voltage steps utilizing a small number of power electric components, as depicted in Table 3 and Figure 7. To efficiently achieve the required output voltage and current, the investigated MLI requires appropriate power devices. Thus, it is necessary to determine their rated power, voltage and current. Since the proposed inverter is built by a multilevel DC-link and three-phase Bridge, it uses switches with different voltage rat- ings, as illustrated in Table 4. Furthermore, it was assumed that all power devices of the inverter have the same current rating. Compared to other multilevel inverters listed in Table 5, the proposed inverter requires high voltage rating switches. As a result of this comparison, the total average cost per switch for the proposed inverter is higher than other NPC, FC, CHB and hybrid multilevel inverter switches, and approximately equal to that calculated in [29,30]. This additional cost can be mostly compensated for, since the proposed inverter requires a lower amount of DC supplies, IGBTs, diodes and gate driv- ers. In general, when matched by additional MLI structures, the proposed MLI’s major benefits are: (1) a higher number of voltage levels applying power components in small numbers, (2) a low-cost heat sink, smaller installation area and low gate drivers being required, (3) inheriting certain benefits of traditional two-level inverters such as a lesser number of control signals, simple operating standard and low conduction loss. It also has similar advantages to multilevel inverters such as reduced switching losses, small har- monic distortions and improved performance. In contrast, the disadvantages are: (1) IGBT switches (Q1~Q6) must sustain the complete DC-link voltage once the MLI generates the maximum voltage ±5Vdc, whereas the bidirectional, half-bridge and full-bridge IGBTs re- quired to sustain ±4Vdc, ±3Vdc and ±Vdc, respectively. As a result, different power ratings on different types of switches are required for building the proposed inverter. (2) Voltage levels (six) in maximum number can only be obtained when the modulation index is greater than 0.98, otherwise the behavior of the MLI becomes akin to a classical two-level inverter. Therefore, the projected MLI is highly appropriate for PV applications working on medium voltage conditions [31] and following fundamental switching frequency at the fixed modulation index Ma > 0.98. Micromachines 2021, 12, 1133 11 of 16 Table 3. Comparative analysis between different multilevel inverter topologies in terms of voltage levels. Components NPC FC CHB [9] [15] Proposed 4 log3 [2/3 (N) − 1] + Switches 6 (N − 1) 6 (N − 1) 6 (N − 1) 2 log2 (N − 1) + 12 12 [log3 (N/2) − 1] + 18 14 4 log3 [2/3 (N) − 1] + Diodes 6 (N − 1) 6 (N − 1) 6 (N − 1) 2 log2 (N − 1) + 12 12 [log3 (N/2) − 1] + 18 14 Clamping diodes 6 (N − 2) 0 0 0 0 0 4 log3 [2/3 (N) − 1] + Gate drivers 6 (N − 1) 6 (N − 1) 6 (N − 1) 2 log2 (N − 1) + 9 12 [log3 (N/2) − 1] + 18 11 DC supplies N−1 N−1 3 (N − 1)/2 1 + log2(N − 1) 3 [log3 (N/2) − 1] + 4 log3 [2/3 (N) − 1] + 2 Capacitors 0 3 (N − 2) 0 0 0 0 Control signals 6 (N − 1) 6 (N − 1) 6 (N − 1) 2 log2 (N − 1) + 9 12 [log3 (N/2) − 1] + 18 4 log3 [2/3 (N) − 1]+11 (a) (b) Figure 7. Comparison in terms of: (a) DC supplies, (b) switches. Table 4. Voltage ratings of proposed topology switches. Switches Main Bridge Bidirectional Half-Bridge Full-Bridge Voltage rating (N − 1) Vdc (N − 2) Vdc 3n (Vdc) 3(n − 1) (Vdc) Table 5. Voltage rating of other multilevel inverter topologies. Voltage Ratings NPC FC CHB [9] [15] Switch Vdc Vdc Vdc (N − 1) Vdc Vdc Diode Vdc 0 0 0 0 Capacitor 0 Vdc 0 0 0 5. Experimental Validation and Results 5.1. Experimental Setup An inverter prototype is built and tested by applying f = 50 Hz and Ma = (1.3, 1.15, 0.98 and 0.8) for validating the compatibility of the studied modulation method and the performance of the proposed inverter, as shown in Figure 8. Three isolated DC voltage supplies having different magnitudes (Vdc = 20 V, 3Vdc = 60 V and 2Vdc = 40 V) are used to form the multilevel DC-link. A three-phase load (237 Ω–0.5 H) is used as the output. The inverter control algorithm based on the suggested modulation technique is developed using Simulink/ MATLAB software and TMS320F28335 DSP controller. Figure 9 illus- trates the proposed MLI’s control diagram. Micromachines 2021, 12, 1133 12 of 16 Figure 8. Laboratory setup of the hardware prototype. Figure 9. Control block diagram. 5.2. Experimental Results The inverter line to ground, line to line, line to neutral, line to center and center to ground outputs are shown in Figure 10. For Ma = 1.3, the waveforms for Vag, Vbg and Vcg have six symmetric voltage levels with the highest value of 100 V, as shown in Figure 10a. It should be addressed that the experimental results are presented following the RGB color format, which means all the waveforms of phase a are represented by red color, while the waveforms of phase b and phase c are represented by a green and blue color, respectively. Vag Vab Vbg Vbc 50V Vcg 50V Vca 0 0 0 2.5 ms 2.5 ms (a) (b) Micromachines 2021, 12, 1133 13 of 16 VaN Vao 20V 20V 2.5 ms 2.5 ms (c) (d) Vab Vag Vog Vbc 20V 50V Vca 2.5 ms 2.5 ms (e) (f) Vab Vab Vbc Vbc 50V 50V Vca Vca 2.5 ms 2.5 ms (g) (h) Figure 10. For Ma =1.3, the MLIs are: (a) line to ground voltages, (b) line to line voltages, (c) line to neutral voltage, (d) line to mid-point voltage and (e) line to ground and mid-point ground voltages, (f) For Ma =1.15, line to line voltages, (g) For Ma = 0.98, line to line voltages, (h) For Ma = 0.8, line to line voltages. The waveforms of Vab, Vbc and Vca are composed of 11 voltage steps with a peak value of 100 V, as depicted by Figure 10b. In Figure 10c, the inverter line to neutral VaN reached its peak value of 63 V with 16 voltage steps, while the waveform of Vao attained the peak voltage of 80 V producing nine voltage levels as shown in Figure 10d. From Fig- ure 10e, four different voltage values are taken from inverter mid-point to ground Vog, with the peak value of 80 V. Then, within a full cycle of Vag, a repetition occurs three times. In Figure 10f,g, the proposed MLI’s line to line output voltage at modulation index, Ma = 1.15 and 0.98 are depicted, respectively. The performance of the proposed MLI be- comes the same as that of a traditional two-level inverter when Ma = 0.8, as shown in Figure 10h. The harmonic spectrum for the waveforms of inverter line to line voltage and load current at Ma = 1 are depicted in Figure 11. According to Figure 11, both spectrums do not contain any triplen harmonics such as 3rd, 9th and 15th harmonics. Furthermore, all even harmonics are eliminated because Micromachines 2021, 12, 1133 14 of 16 the MLI’s output voltage and load current have obtained symmetry. %THD for the load current is only 5.8%, while the THD for MLI’s line to line voltage is 12.3%. 1st 5th 7th 13th 17th 19th 1st 5th 7th 17th Figure 11. Harmonic spectrum of load current (yellow) and line to line voltage (green). 6. Conclusions A novel three-phase six-level multilevel inverter structure was developed and is out- lined in this manuscript. The designed MLI possesses some advantageous characteristics topology such as it requires the least amount of power components and DC supplies, the prototype can be built-in cost-effective manner and it can be controlled using a simple modulation technique. A new approach based on the nearest vector modulation technique was easily implemented and the switching gate signals were successfully generated. Fur- thermore, a three-phase N-level structure based on the proposed configuration was sug- gested and discussed. The proposed MLI validity and suggested modulation technique compatibility was validated by employing both experimental and simulation approaches. The simple and pragmatic design of the proposed MLI would make it a highly suitable candidate for medium voltage applications in distributed renewable energy applications and grid-connected systems. The low current THD and higher efficiency generated by the MLI will allow it to be utilized in various industrial applications. The concluding remarks of the manuscript can be listed as follows: 1. The proposed MLI utilized a reduced number of power electric components com- pared to classical and other recently developed MLIs. 2. The modularity of the MLI makes it a suitable candidate for high voltage operations. 3. The operating efficiency of the MLI is 97.59% and effectively follows the IEEE 1547 standard, making it suitable to be applied as an interconnected device in grid sys- tems. 4. The low current THD of 5.8% would allow this inverter to be utilized in the grid’s current and voltage compensation systems, including shunt active power filters (SAPFs), voltage restorers and unified power quality conditioners (UPQCs). Author Contributions: Conceptualization, S.T.M. and A.M.; methodology, S.T.M. and A.M.; formal analysis, S.T.M., A.M. and K.H.; investigation, S.T.M., K.H. and N.Z.Y.; resources, S.T.M., A.M. and N.Z.Y.; data curation, S.T.M., A.M., K.H. and F.M.; writing—original draft preparation, S.T.M., A.M. and K.H.; writing—review and editing, M.S.H.L., S.H.M.A., A.H. and M.M.O.; supervision, M.S.H.L.; project administration, M.S.H.L.; funding acquisition, M.S.H.L. All authors have read and agreed to the published version of the manuscript. Micromachines 2021, 12, 1133 15 of 16 Funding: This work was supported by Universiti Kebangsaan Malaysia under Grant Code GP-2021- K023221. Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable. Data Availability Statement: Not applicable. Conflicts of Interest: The authors declare no conflict of interest. References 1. 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