RISC-V - Debian Wiki
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RISC-V
This page contains details about a port of Debian for the RISC-V architecture called
riscv64
, see
riscv64 port
. For 32 bit (riscv32) see
32 bit RISC-V
Contents
In a nutshell
What is RISC-V?
What is a Debian port?
What are the goals of this project in particular?
Summary
Progress
Upstream project / Architecture
Upstream project / Community
Architecture details
Toolchain upstreaming status
Hardware
SBC overview by SoC
🟦 StarFive: JH7110 SoC (Core: SiFive U74, GPU: Imagination IMG BXE-4-32)
🟩 SpacemiT: K1 SoC (Core: SpacemiT X60, GPU: Imagination IMG BXE-2-32, with RVV 1.0)
🟥 Alibaba T-Head: TH1520 SoC (Core: XuanTie C910, GPU: Imagination IMG BXM-4-64)
🟨 ESWIN: EIC7700X SoC (Core: SiFive P550, GPU: Imagination IMG AXM-8-256)
Popular SBCs
StarFive VisionFive 2 board with JH7110 SoC
Sipeed Lichee Pi4 board
BeagleV-Ahead, T-Head TH1520 SoC, 4 C910 cores
Lichee RV
Mango Pi MQ Pro
Nezha
SiFive "Freedom U540" SoC (quad-core RV64GC) / "HiFive Unleashed"
Microchip "PolarFire SoC FPGA" / "PolarFire SoC FPGA Icicle Kit" (MPFS-ICICLE-KIT-ES)
SiFive "Freedom U740" SoC / "HiFive Unmatched"
StarFive VisionFive board with JH7100 SoC
Framework 13 RISC-V Mainboard V1 (fml13v01)
Planned
Debian port information
Hardware baseline and ABI choice
Resources
Mailing list
IRC
Bugs (BTS)
FTBFS, packages that Fail To Build From Source (in riscv64)
Cross compilation
Pre-built toolchains
Using pre-built toolchains with sbuild
Building a toolchain with rebootstrap
Qemu
Installing qemu from the Debian archive
Manual qemu-user installation
Package repository
Creating a riscv64 chroot
mmdebstrap
debootstrap
Preparing the chroot for use in a virtual machine
Setting up a riscv64 virtual machine
buildd (build-daemon) information
Porterboxes
OS / filesystem images
Status Log
Credits
History
In a nutshell
What is RISC-V?
From the
Wikipedia entry for RISC-V
RISC-V (pronounced "risk-five") is an open source instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.
In contrast to most ISAs, RISC-V is freely available for all types of use, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency. The instruction set also has a substantial body of supporting software, which fixes the usual weakness of new instruction sets.
The project was originated in 2010 by researchers in the Computer Science Division at UC Berkeley, but many contributors are volunteers and industry workers that are unaffiliated with the university.
There are different versions of the instruction set for 32, 64 and 128 bits; operating as little-endian by default.
What is a Debian port?
In short, a
port
in Debian terminology means to provide the software normally available in the Debian archive (over 30,000 source packages) ready to install and run on systems based in a given computer architecture with the
Linux
kernel, or kernel-architecture combinations, with other kernels including
GNU Mach
(from GNU/Hurd) and
kFreeBSD
(from GNU/kFreeBSD).
See
and
Ports
for more information.
What are the goals of this project in particular?
In this project the goal is to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA:
Software-wise, this port targets the
Linux
kernel
Hardware-wise, the port targets the
64-bit
variant,
little-endian
This ISA variant is the "default flavour" recommended by the designers, and the one that seems to attract more interest for planned implementations that might become available in the next few years (development boards, possible consumer hardware or servers).
While 32-bit and 128-bit implementations are possible, there are problems with this:
In the context of RISC-V design, these have not been explored as deeply, and tools and resources (e.g. simulators, research cores) are not as well studied and adapted;
For general purpose computers, the focus shifted to 64-bit for many years already, and there isn't a lot of interest in 32-bit architectures except for specific purposes;
32-bit ports in Debian already struggle to compile some large packages of the archive in the last few months/years, a problem that will become worse with time;
A 128-bit port is simply not realistic at this time.
Summary
See
Ports/riscv64
riscv64 is now an official architecture
Progress
Percentage of packages that build on RISC-V (magenta line)
RISC-V (
last modified 2026-04-03 03:38:45
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