Support RAJA and Scientific Applications on RVV Architectures - RISC-V International
Close Search
Featured Work
Support RAJA and Scientific Applications on RVV Architectures
By
RISC-V International Staff
February 17, 2026
No Comments
3 min read
Project Snapshot
In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. RAJA is a C++ library primarily developed at Lawrence Livermore National Laboratory that offers loop-based abstractions and multiple execution backends to deliver portable performance across heterogeneous systems. We contribute a new RVV backend to RAJA’s vectorization API, enabling RVV-aware optimizations within RAJA-based applications.
In Their Own Words
Poster Preview
Want to Dive Deeper?
Read the full paper on the author’s site
Continue Reading
Meet the Authors
Hung-Ming Lai
PhD Student in Computer Science at National Tsing Hua University in Taiwan
Hung-Ming is a PhD student in the Department of Computer Science, National Tsing-Hua University, Taiwan. His thesis advisor is Prof. Jenq-Kuen Lee. His research interests are in compiler optimizations on RISC-V with SIMD computations, AI compiler optimizations, and compiler analysis for program reliability.
Pei-Hung Lin
Computer Scientist
at
Lawrence Livermore National Laboratory in the USA
Dr. Pei-Hung Lin is a computer scientist in the Center for Applied Scientific Computing (CASC) at Lawrence Livermore National Laboratory (LLNL). His research expertise spans compiler optimizations, parallel programming models, and the integration of machine learning techniques into high-performance computing (HPC) workflows. He received his Ph.D. in Computer Science from the University of Minnesota.
Shou-Chen Chiu
Master’s Student in Computer Science at National Tsing Hua University in Taiwan
Shou-Chen is a graduate student in the Department of Computer Science at National Tsing Hua University, advised by Prof. Jenq-Kuen Lee. His research interests are in compiler optimization on RVV and AI compiler optimization.
Chih-Hsi Lee
Master’s Student in Computer Science
at National Tsing Hua University in Taiwan
Chih-Hsi is a master’s student in the Department of Computer Science, National Tsing-Hua University, Taiwan. His advisor is Prof. Jenq-Kuen Lee. His research focuses on register optimizations for RVV and compiler optimizations on RISC-V.
Jenq-Kuen Lee
Professor at National Tsing Hua University in Taiwan
Jenq‑Kuen Lee is a Professor of Computer Science at National Tsing Hua University, Taiwan, specializing in optimizing compilers. He co‑authored Auto‑tuning Fixed‑point Precision with TVM on RISC‑V Packed SIMD (ACM TODAES 2023) and TVM Hybrid‑OP Optimization on RISC‑V SIMD (IEEE Access 2024). His team enhanced SIMDe to automate ARM NEON‑to‑RVV. He presented the RISC‑V ISA for sub‑FP8 at RISC‑V Summit 2024 and maintained contributions across the RISC‑V GitHub ecosystems and TVM upstream on RVV.
Related Posts
Featured Work
Using a Performance Model to Implement a Superscalar CVA6
Using a Performance Model to Implement a Superscalar CVA6
RISC-V International Staff
March 24, 2026
Featured Work
How We’re Using AI to Streamline RISC-V Regression Debugging
How We’re Using AI to Streamline RISC-V Regression Debugging
RISC-V International Staff
January 27, 2026
Featured Work
Ocelot3: Full Vector “V” Extension for BOOM
Ocelot3: Full Vector “V” Extension for BOOM
RISC-V International Staff
December 10, 2025
Subscribe for updates, event info, webinars, and the latest community news
About
Technical Steering Committee
Board of Directors
FAQ
About RISC-V
History of RISC-V
Blog
News
Announcements
Genealogy
Policies
Code of Conduct
Antitrust Policy
Brand Guidelines
Specification
Ratified
Under Development
Contribute
Developers
Get Started
Training
Development Partners
Developer Boards
Labs
Mentorship
Technical Wiki
Industries
Automotive
Artificial Intelligence
Case Studies
Exchange
Landscape
Software Ecosystem Dashboard
Events
RISC-V Summit
Calendar
Videos
Community Meetings
Members
Current Members
Resources
Recognition
Resources
Get RISC-V Gear
Join RISC-V International
Becoming a member of RISC-V International allows companies and individuals to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs.
JOIN NOW
Copyright © RISC-V International®. All rights reserved. RISC-V, RISC-V International, and the RISC-V logos are trademarks of RISC-V International.
For trademark usage guidelines, please see our
Brand Guidelines
and
Code of Conduct Policy
Antitrust Policy
Close Menu
Blog
Blog Home
News and Updates
Viewpoints
Featured Work
Submit Content
About
Annual Report 2025
About RISC-V International
Staff
Board of Directors
Technical Steering Committee
FAQ
Specifications
Ratified
Specs Under Development
Contribute
Developers
Get Started
Development Partners
Developer Boards
Ecosystem Labs
Technical Meeting Calendar
Technical Resources
Ambassadors & Advocates
Technical Committees & Groups
Industries
Applications
Applications
Automotive
Data Center
High Performance Computing (HPC)
IoT/Embedded
Industrial & Robotics
Space and Aerospace
Technologies
Technologies
Artificial Intelligence
Security
Solutions
Solutions
Case Studies
Exchange
Landscape
Software Ecosystem Dashboard
Community
Events
Events
RISC-V Summits
World RISC-V Days
Calendar
Community Events
Videos
Participate
Participate
Become a RISC-V Insider
Meeting Calendar
Alliances
Marketing Committees & Groups
Forums
Job Board
Learn
Learn
Training
Training Partners
Mentorship
Teach a Course
Membership
Current Members
Join
Resources
Recognition
x-twitter
github
flickr
slack
email